Clarify misleading text in Zifencei chapter

As the instruction's definition states, it orders stores that are visible
with subsequent fetches.  By definition, this includes a subset of other
hart's stores.  Yet, some other text may lend the impression to the reader
that it only orders the current hart's stores.

1 files changed, 5 insertions, 5 deletions

diff --git a/src/zifencei.tex b/src/zifencei.tex
index d152c6d..fc8b067 100644
--- a/src/zifencei.tex
+++ b/src/zifencei.tex
@@ -5,8 +5,8 @@ This chapter defines the ``Zifencei'' extension, which includes the
 FENCE.I instruction that provides explicit synchronization between
 writes to instruction memory and instruction fetches on the same hart.
 Currently, this instruction is the only standard mechanism to ensure
-an instruction modified by a store on a hart will be visible to a
-subsequent instruction fetch on the same hart.
+that stores visible to a hart will also be visible to its instruction
+fetches.
 
 \begin{commentary}
 We considered but did not include a ``store instruction word''
@@ -85,9 +85,9 @@ ABI that relies on machine-mode cache-maintenance operations.
 
 The FENCE.I instruction is used to synchronize the instruction and
 data streams.  RISC-V does not guarantee that stores to instruction
-memory will be made visible to instruction fetches on the same RISC-V
-hart until a FENCE.I instruction is executed.  A FENCE.I instruction
-only ensures that a subsequent instruction fetch on a RISC-V hart
+memory will be made visible to instruction fetches on a RISC-V
+hart until that hart executes a FENCE.I instruction.  A FENCE.I instruction
+ensures that a subsequent instruction fetch on a RISC-V hart
 will see any previous data stores already visible to the same RISC-V
 hart.  FENCE.I does {\em not} ensure that other RISC-V harts'
 instruction fetches will observe the local hart's stores in a