diff options
| author | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 00:07:46 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-06-25 00:18:57 -0700 |
| commit | 4eeaf69b4afcb711be566f98cbe19425c6a6cc49 (patch) | |
| tree | 4a145f195a073a50aace72f8af1709449a2fa378 /src | |
| parent | 6993896ac6824b7c7559b7f41ecaa0daf77a8cbe (diff) | |
| download | riscv-isa-manual-4eeaf69b4afcb711be566f98cbe19425c6a6cc49.zip riscv-isa-manual-4eeaf69b4afcb711be566f98cbe19425c6a6cc49.tar.gz riscv-isa-manual-4eeaf69b4afcb711be566f98cbe19425c6a6cc49.tar.bz2 | |
Indicate that mcycle can be shared between harts
When reading through the manual for the QEMU patches to implement
mcounterinhibit I found that the commentary allows mcycle to be shared
between harts. I actually really don't like this behavior, but I can
understand that it may make sense for some systems. Regardless, the
normative text of the ISA manual should match the commentary.
This patch introduces the concept that modifications of a CSR on one
hart may cause the value on other harts to change. If I understand
correctly that's not quite a WARL field, which can only change upon
writes. I don't think it's worth giving this a name, though, as
hopefull it'll only apply to mcycle.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index 302a620..9bbb48b 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1698,7 +1698,9 @@ precision on all RV32 and RV64 systems. The counter registers have an arbitrary value after system reset, and can be written with a given value. Any CSR write takes effect after -the writing instruction has otherwise completed. +the writing instruction has otherwise completed. Writes to {\tt mcycle} on one +hart may change the value of {\tt mcycle} on other harts, the platform must +provide a mechanism to indicate when this behavior will occur. The hardware performance monitor includes 29 additional 64-bit event counters, {\tt mhpmcounter3}--{\tt mhpmcounter31}. The event selector CSRs, {\tt @@ -1907,7 +1909,9 @@ their accessibility is not affected by the setting of this register. When the CY, IR, or HPM{\em n} bit in the {\tt mcountinhibit} register is clear, the {\tt cycle}, {\tt instret}, or {\tt hpmcounter{\em n}} register increments as usual. When the CY, IR, or HPM{\em n} bit is set, the -corresponding counter does not increment. +corresponding counter does not increment. Writes to {\tt mcountinhibit}.CY may +change the value of {\tt mcountintihib}.CY on other harts, the platform must +provide a mechanism to indicate when this behavior will occur. If the {\tt mcountinhibit} register is not implemented, the implementation behaves as though the register were set to zero. |