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| author | Andrew Waterman <andrew@sifive.com> | 2019-06-21 15:10:16 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-06-21 16:49:26 -0700 |
| commit | 1e8c2e1fc2c1fd4a5b9177869aee8ace4b5879bb (patch) | |
| tree | 578825dc700e53db0d6fcb309c9cb14ac8d34d4d /src | |
| parent | a81b0a0cf2e2846a6af9f6a492780bec72baa5f3 (diff) | |
| download | riscv-isa-manual-1e8c2e1fc2c1fd4a5b9177869aee8ace4b5879bb.zip riscv-isa-manual-1e8c2e1fc2c1fd4a5b9177869aee8ace4b5879bb.tar.gz riscv-isa-manual-1e8c2e1fc2c1fd4a5b9177869aee8ace4b5879bb.tar.bz2 | |
Bump version of unprivileged spec to 20190621-draft
Diffstat (limited to 'src')
| -rw-r--r-- | src/preface.tex | 50 | ||||
| -rw-r--r-- | src/riscv-spec.tex | 4 |
2 files changed, 52 insertions, 2 deletions
diff --git a/src/preface.tex b/src/preface.tex index d908c55..2a5a539 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -1,5 +1,55 @@ \chapter{Preface} +This document describes the RISC-V unprivileged architecture. + +The ISA modules marked Ratified have been ratified at this time. The modules +marked {\em Frozen} are not expected to change significantly before being put +up for ratification. The modules marked {\em Draft} are expected to change +before ratification. + +The document contains the following versions of the RISC-V ISA modules: + +{ +\begin{table}[hbt] + \centering + \begin{tabular}{|c|l|c|} + \hline + Base & Version & Status\\ + \hline + RVWMO & 2.0 & \bf Ratified \\ + \bf RV32I & \bf 2.1 & \bf Ratified \\ + \bf RV64I & \bf 2.1 & \bf Ratified \\ + \em RV32E & \em 1.9 & \em Draft \\ + \em RV128I & \em 1.7 & \em Draft \\ + \hline + Extension & Version & Status \\ + \hline + \bf Zifencei & \bf 2.0 & \bf Ratified \\ + \bf Zicsr & \bf 2.0 & \bf Ratified \\ + \bf M & \bf 2.0 & \bf Ratified \\ + \em A & \em 2.0 & Frozen \\ + \bf F & \bf 2.2 & \bf Ratified \\ + \bf D & \bf 2.2 & \bf Ratified \\ + \bf Q & \bf 2.2 & \bf Ratified \\ + \bf C & \bf 2.0 & \bf Ratified \\ + \em Ztso & \em 0.1 & \em Frozen \\ + \em Counters & \em 2.0 & \em Draft \\ + \em L & \em 0.0 & \em Draft \\ + \em B & \em 0.0 & \em Draft \\ + \em J & \em 0.0 & \em Draft \\ + \em T & \em 0.0 & \em Draft \\ + \em P & \em 0.2 & \em Draft \\ + \em V & \em 0.7 & \em Draft \\ + \em N & \em 1.1 & \em Draft \\ + \em Zam & \em 0.1 & \em Draft \\ + \hline + \end{tabular} +\end{table} +} + + +\section*{Preface to Document Version 20190608-Base-Ratified} + This document describes the RISC-V unprivileged architecture. The RVWMO memory model has been ratified at this time. The ISA diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex index a690904..1d4bd7f 100644 --- a/src/riscv-spec.tex +++ b/src/riscv-spec.tex @@ -10,8 +10,8 @@ \input{preamble} -\newcommand{\specrev}{\mbox{20190608-Base-Ratified}} -\newcommand{\specmonthyear}{\mbox{March 2019}} +\newcommand{\specrev}{\mbox{20190621-{\em draft}}} +\newcommand{\specmonthyear}{\mbox{June 2019}} \begin{document} |