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| author | Andrew Waterman <andrew@sifive.com> | 2019-04-20 19:47:20 -0500 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-04-20 19:47:20 -0500 |
| commit | 0977e031f50aa838eae3ae66922bb5b8c19a4333 (patch) | |
| tree | 7c18508629ca0235766dfa8b5ae1808adc72eaa6 /src | |
| parent | a5df328724f5b769b4c5941625871cc280b84604 (diff) | |
| download | riscv-isa-manual-0977e031f50aa838eae3ae66922bb5b8c19a4333.zip riscv-isa-manual-0977e031f50aa838eae3ae66922bb5b8c19a4333.tar.gz riscv-isa-manual-0977e031f50aa838eae3ae66922bb5b8c19a4333.tar.bz2 | |
Express stvec alignment constraint more clearly
Diffstat (limited to 'src')
| -rw-r--r-- | src/supervisor.tex | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 0c964bd..6be18a1 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -266,11 +266,10 @@ SXLEN-2 & 2 \\ \label{stvecreg} \end{figure*} -The BASE field in {\tt stvec} is a \warl\ field that can hold any valid virtual -or physical address, subject to the following alignment constraints: the -address must always be at least 4-byte aligned, and the MODE -setting may impose additional alignment constraints on the value in the BASE -field. +The BASE field in {\tt stvec} is a \warl\ field that can hold any valid +virtual or physical address, subject to the following alignment constraints: +the address must be 4-byte aligned, and MODE settings other than Direct might +impose additional alignment constraints on the value in the BASE field. \begin{table*}[h!] \begin{center} |