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| author | Andrew Waterman <andrew@sifive.com> | 2019-10-06 21:54:46 +0200 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-10-06 21:54:46 +0200 |
| commit | da9b0752dbe570cf0493f4c7eb790ace845896af (patch) | |
| tree | 9939e83079beffbf5de87d50b49393006fc2005b /src | |
| parent | ef917313d97d89b43a799d0ed12193b498c233f5 (diff) | |
| download | riscv-isa-manual-da9b0752dbe570cf0493f4c7eb790ace845896af.zip riscv-isa-manual-da9b0752dbe570cf0493f4c7eb790ace845896af.tar.gz riscv-isa-manual-da9b0752dbe570cf0493f4c7eb790ace845896af.tar.bz2 | |
Incorporate Anthony Coulter's feedback
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/6rpIanfXCVc/SIp_dwvCAgAJ
Diffstat (limited to 'src')
| -rw-r--r-- | src/a.tex | 7 |
1 files changed, 4 insertions, 3 deletions
@@ -458,9 +458,10 @@ be discarded by writing to {\tt x0}. \begin{commentary} We provided fetch-and-op style atomic primitives as they scale to -highly parallel systems better than LR/SC or CAS. A simple -microarchitecture can implement AMOs using the LR/SC primitives. More -complex implementations might also implement AMOs at memory +highly parallel systems better than LR/SC or CAS. +A simple microarchitecture can implement AMOs using the LR/SC primitives, +provided the implementation can guarantee the AMO eventually completes. +More complex implementations might also implement AMOs at memory controllers, and can optimize away fetching the original value when the destination is {\tt x0}. |