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author | Andrew Waterman <andrew@sifive.com> | 2021-09-15 18:26:02 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2021-09-15 18:26:02 -0700 |
commit | 85893aaebb86efa13e5502bc7f5f3c57358bcbff (patch) | |
tree | 450ed1adf284682170e6f2a0abe15d7d9ff116f5 /src | |
parent | aba1ff8c2439b3ad4fb491f3c06f24e3cf9ee65b (diff) | |
download | riscv-isa-manual-85893aaebb86efa13e5502bc7f5f3c57358bcbff.zip riscv-isa-manual-85893aaebb86efa13e5502bc7f5f3c57358bcbff.tar.gz riscv-isa-manual-85893aaebb86efa13e5502bc7f5f3c57358bcbff.tar.bz2 |
RISC-V Foundation -> RISC-V International
Diffstat (limited to 'src')
-rw-r--r-- | src/intro.tex | 4 | ||||
-rw-r--r-- | src/machine.tex | 10 | ||||
-rw-r--r-- | src/priv-preface.tex | 2 | ||||
-rw-r--r-- | src/riscv-privileged.tex | 2 | ||||
-rw-r--r-- | src/riscv-spec.tex | 2 |
5 files changed, 10 insertions, 10 deletions
diff --git a/src/intro.tex b/src/intro.tex index 4acdd42..330902b 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -311,8 +311,8 @@ For this purpose, we divide each RISC-V instruction-set encoding space (and related encoding spaces such as the CSRs) into three disjoint categories: {\em standard}, {\em reserved}, and {\em custom}. Standard extensions and encodings -are defined by the Foundation; any extensions not defined by the -Foundation are {\em non-standard}. +are defined by RISC-V International; any extensions not defined by +RISC-V International are {\em non-standard}. Each base ISA and its standard extensions use only standard encodings, and shall not conflict with each other in their uses of these encodings. Reserved encodings are currently not defined but are saved for future diff --git a/src/machine.tex b/src/machine.tex index 5d0d60e..3472d44 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -231,8 +231,8 @@ that is one less than the JEDEC bank number. \end{commentary} \begin{commentary} -Previously the vendor ID was to be a number allocated by the RISC-V -Foundation, but this duplicates the work of JEDEC in maintaining a +Previously the vendor ID was to be a number allocated by RISC-V +International, but this duplicates the work of JEDEC in maintaining a manufacturer ID standard. At time of writing, registering a manufacturer ID with JEDEC has a one-time cost of \$500. \end{commentary} @@ -263,8 +263,8 @@ MXLEN \\ \label{marchreg} \end{figure*} -Open-source project architecture IDs are allocated globally by the -RISC-V Foundation, and have non-zero architecture IDs with a zero +Open-source project architecture IDs are allocated globally by +RISC-V International, and have non-zero architecture IDs with a zero most-significant-bit (MSB). Commercial architecture IDs are allocated by each commercial vendor independently, but must have the MSB set and cannot contain zero in the remaining MXLEN-1 bits. @@ -276,7 +276,7 @@ occurs rather than a particular organization. Commercial fabrications of open-source designs should (and might be required by the license to) retain the original architecture ID. This will aid in reducing fragmentation and tool support costs, as well as provide attribution. -Open-source architecture IDs should be administered by the Foundation +Open-source architecture IDs are administered by RISC-V International and should only be allocated to released, functioning open-source projects. Commercial architecture IDs can be managed independently by any registered vendor but are required to have IDs disjoint from the diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 6a543b9..4e59093 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -21,7 +21,7 @@ modules: } The Machine and Supervisor ISAs, version 1.11, have been ratified by -the RISC-V Foundation. Version 1.12 of these modules, described in +RISC-V International. Version 1.12 of these modules, described in this document, is a minor revision to version 1.11. The following changes have been made since version 1.11, which, while not diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex index 9933ae8..9074de0 100644 --- a/src/riscv-privileged.tex +++ b/src/riscv-privileged.tex @@ -57,7 +57,7 @@ Creative Commons Attribution 4.0 International License. Please cite as: ``The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version \privrev'', Editors -Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \privmonthyear. +Andrew Waterman and Krste Asanovi\'{c}, RISC-V International, \privmonthyear. \markboth{Volume II: RISC-V Privileged Architectures V\privrev} {Volume II: RISC-V Privileged Architectures V\privrev} diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex index a67cfd8..1b0e3b6 100644 --- a/src/riscv-spec.tex +++ b/src/riscv-spec.tex @@ -59,7 +59,7 @@ Creative Commons Attribution 4.0 International License. Please cite as: ``The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version \specrev'', Editors -Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \specmonthyear. +Andrew Waterman and Krste Asanovi\'{c}, RISC-V International, \specmonthyear. \markboth{Volume I: RISC-V Unprivileged ISA V\specrev} |