Fix editing error in mtval/stval definition

Partially introduced by 7f45777bfc3e0a6b327552a286392ccfd5c933a8 and 94ab414c4b470edae8bde4e7759163fe7ddf8ab4

The spec says that the platform will define which exceptions must populate
mtval or stval with a nonzero value and which are permitted to zero it.
But then later statements seem not to permit the possibility of zeroing
the register, which is a contradiction.  Resolve in a backwards-compatible
manner by permitting zeros unless the platform says otherwise (which was
the original intent, anyway).

This permits e.g. zeroing mtval on an EBREAK instruction, where mepc
provides sufficient information, as was the intent of 94ab414c4b470edae8bde4e7759163fe7ddf8ab4.

2 files changed, 53 insertions, 71 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 2ae1756..93b16e4 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2154,25 +2154,12 @@ which may unconditionally set it to zero.
 If the hardware platform specifies that no exceptions set {\tt mtval} to a
 nonzero value, then {\tt mtval} is hardwired to zero.
 
-If {\tt mtval} is not hardwired to zero, then when a breakpoint,
-address-misaligned, access-fault, or page-fault exception occurs
-on an instruction fetch, load, or store, {\tt
-  mtval} is written with the faulting virtual address.  On an illegal
-instruction trap, {\tt mtval} may be written with the first XLEN or ILEN
-bits of the faulting instruction as described below.  For other traps,
-{\tt mtval} is set to zero, but a future standard may redefine {\tt
-  mtval}'s setting for other traps.
+If {\tt mtval} is written with a nonzero value when a breakpoint,
+address-misaligned, access-fault, or page-fault exception occurs on an
+instruction fetch, load, or store, then {\tt mtval} will contain the faulting
+virtual address.
 
 \begin{commentary}
-  The {\tt mtval} register replaces the {\tt mbadaddr} register in
-  the previous specification.  In addition to providing bad addresses,
-  the register can now provide the bad instruction that triggered an
-  illegal instruction trap (and may in future be used to return other
-  information).  Returning the instruction bits accelerates instruction emulation and also
-  removes some races that might be present when trying to emulate
-  illegal instructions.
-\end{commentary}
-\begin{commentary}
   When page-based virtual memory is enabled, {\tt mtval} is written with
   the faulting virtual address, even for physical-memory access-fault exceptions.
   This design reduces datapath cost for most implementations, particularly
@@ -2196,32 +2183,28 @@ MXLEN \\
 \label{mtvalreg}
 \end{figure}
 
-For misaligned loads and stores that cause access-fault or page-fault exceptions,
-{\tt mtval} will contain the virtual address of the portion of the access that
-caused the fault (unless {\tt mtval} is hardwired to zero).
-
-For instruction access-fault or page-fault exceptions on
-systems with variable-length instructions, {\tt mtval} will contain the
-virtual address of the portion of the instruction that caused the fault
-(unless {\tt mtval} is hardwired to zero).
-{\tt mepc} will point to the beginning of the instruction.
-
-The {\tt mtval} register can optionally also be used to return the
-faulting instruction bits on an illegal instruction exception ({\tt
-  mepc} points to the faulting instruction in memory).
-
-If this feature is not provided, then {\tt mtval} is set to zero on
-an illegal instruction fault.
-
-If this feature is provided, after an illegal instruction trap, {\tt mtval}
-will contain the shortest of:
+If {\tt mtval} is written with a nonzero value when a misaligned load or store
+causes an access-fault or page-fault exception, then {\tt mtval} will contain
+the virtual address of the portion of the access that caused the fault.
+
+If {\tt mtval} is written with a nonzero value when an instruction
+access-fault or page-fault exception occurs on a system with variable-length
+instructions, then {\tt mtval} will contain the virtual address of the portion
+of the instruction that caused the fault, while {\tt mepc} will point to the
+beginning of the instruction.
+
+The {\tt mtval} register can optionally also be used to return the faulting
+instruction bits on an illegal instruction exception ({\tt mepc} points to the
+faulting instruction in memory).
+If {\tt mtval} is written with a nonzero value when an illegal-instruction
+exception occurs, then {\tt mtval} will contain the shortest of:
 \begin{compactitem}
 \item the actual faulting instruction
 \item the first ILEN bits of the faulting instruction
-\item the first XLEN bits of the faulting instruction
+\item the first MXLEN bits of the faulting instruction
 \end{compactitem}
-The value loaded into {\tt mtval} is right-justified and all unused upper
-bits are cleared to zero.
+The value loaded into {\tt mtval} on an illegal-instruction exception is
+right-justified and all unused upper bits are cleared to zero.
 
 \begin{commentary}
   Capturing the faulting instruction in {\tt mtval} reduces the
@@ -2233,7 +2216,7 @@ bits are cleared to zero.
   instruction memory, as might occur in a dynamic translation system.
 
   A requirement is that the entire instruction (or at least the first
-  XLEN bits) are fetched into {\tt mtval} before taking the trap.
+  MXLEN bits) are fetched into {\tt mtval} before taking the trap.
   This should not constrain implementations, which would typically
   fetch the entire instruction before attempting to decode the
   instruction, and avoids complicating software handlers.
@@ -2246,6 +2229,9 @@ bits are cleared to zero.
   appropriate trap handling before runtime).
 \end{commentary}
 
+For other traps, {\tt mtval} is set to zero, but a future standard may
+redefine {\tt mtval}'s setting for other traps.
+
 If {\tt mtval} is not hardwired to zero, it is a \warl\ register that must be
 able to hold all valid virtual addresses and the value zero.
 It need not be capable of holding all
@@ -2254,7 +2240,7 @@ Prior to writing {\tt mtval}, implementations may convert an invalid address
 into some other invalid address that {\tt mtval} is capable of holding.
 If the feature to return the faulting instruction bits is implemented, {\tt
 mtval} must also be able to hold all values less than $2^N$, where $N$ is the
-smaller of XLEN and ILEN.
+smaller of MXLEN and ILEN.
 
 \subsection{Machine Configuration Pointer Register ({\tt mconfigptr})}
 
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 83866df..bac284d 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -736,14 +736,10 @@ which exceptions must set {\tt stval} informatively and which may
 unconditionally set it to zero.
 
 
-When a breakpoint,
-address-misaligned, access-fault, or page-fault exception occurs
-on an instruction fetch, load, or store, {\tt stval}
-is written with the faulting virtual address.  On an illegal instruction trap,
-{\tt stval} may be written with the first XLEN or ILEN bits of the faulting
-instruction as described below.  For other exceptions, {\tt stval} is set to
-zero, but a future standard may redefine {\tt stval}'s setting for other
-exceptions.
+If {\tt stval} is written with a nonzero value when a breakpoint,
+address-misaligned, access-fault, or page-fault exception occurs on an
+instruction fetch, load, or store, then {\tt stval} will contain the faulting
+virtual address.
 
 \begin{figure}[h!]
 {\footnotesize
@@ -762,31 +758,31 @@ SXLEN \\
 \label{stvalreg}
 \end{figure}
 
-For misaligned loads and stores that cause access-fault or page-fault
-exceptions, {\tt stval} will contain the virtual address of the
-portion of the access that caused the fault.  For
-instruction access-fault or page-fault exceptions on systems
-with variable-length instructions, {\tt stval} will contain the
-virtual address of the portion of the instruction that caused
-the fault while {\tt sepc} will point to the beginning of the
-instruction.
-
-The {\tt stval} register can optionally also be used to return the
-faulting instruction bits on an illegal instruction exception ({\tt
-  sepc} points to the faulting instruction in memory).
-
-If this feature is not provided, then {\tt stval} is set to zero on
-an illegal instruction fault.
-
-If this feature is provided, after an illegal instruction trap, {\tt stval}
-will contain the shortest of:
+If {\tt stval} is written with a nonzero value when a misaligned load or store
+causes an access-fault or page-fault exception, then {\tt stval} will contain
+the virtual address of the portion of the access that caused the fault.
+
+If {\tt stval} is written with a nonzero value when an instruction access-fault
+or page-fault exception occurs on a system with variable-length instructions,
+then {\tt stval} will contain the virtual address of the portion of the
+instruction that caused the fault, while {\tt sepc} will point to the beginning
+of the instruction.
+
+The {\tt stval} register can optionally also be used to return the faulting
+instruction bits on an illegal instruction exception ({\tt sepc} points to the
+faulting instruction in memory).
+If {\tt stval} is written with a nonzero value when an illegal-instruction
+exception occurs, then {\tt stval} will contain the shortest of:
 \begin{compactitem}
 \item the actual faulting instruction
 \item the first ILEN bits of the faulting instruction
-\item the first XLEN bits of the faulting instruction
+\item the first SXLEN bits of the faulting instruction
 \end{compactitem}
-The value loaded into {\tt stval} is right-justified and all unused upper
-bits are cleared to zero.
+The value loaded into {\tt stval} on an illegal-instruction exception is
+right-justified and all unused upper bits are cleared to zero.
+
+For other traps, {\tt stval} is set to zero, but a future standard may
+redefine {\tt stval}'s setting for other traps.
 
 {\tt stval} is a \warl\ register that must be able to hold all valid
 virtual addresses and the value 0.  It need not be capable of holding all
@@ -795,7 +791,7 @@ Prior to writing {\tt stval}, implementations may convert an invalid address
 into some other invalid address that {\tt stval} is capable of holding.
 If the feature to return the faulting instruction bits is implemented, {\tt
 stval} must also be able to hold all values less than $2^N$, where $N$ is the
-smaller of XLEN and ILEN.
+smaller of SXLEN and ILEN.
 
 \subsection{Supervisor Environment Configuration Register ({\tt senvcfg})}