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| author | Andrew Waterman <andrew@sifive.com> | 2021-10-28 13:11:31 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-10-28 13:11:31 -0700 |
| commit | 2355037df3035451ea67029810a75d1d423c9f66 (patch) | |
| tree | e175d1dbf5e29c8de282d6b6b6a608faf036839f /src | |
| parent | dbdea6b06f031a500a4c8ff3fcd52d0dfab2574e (diff) | |
| download | riscv-isa-manual-2355037df3035451ea67029810a75d1d423c9f66.zip riscv-isa-manual-2355037df3035451ea67029810a75d1d423c9f66.tar.gz riscv-isa-manual-2355037df3035451ea67029810a75d1d423c9f66.tar.bz2 | |
Incorporate Steve's feedback
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index a5e7037..361d6c6 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -100,7 +100,7 @@ extensions, and I shall be selected over E if both are available. When a standard extension is disabled by clearing its bit in {\tt misa}, the instructions and CSRs defined or modified by the extension revert to their defined or reserved behaviors as if the extension is not implemented. -The RV128I base ISA is not yet frozen, and while much of the remainder of this +The design of the RV128I base ISA is not yet complete, and while much of the remainder of this specification is expected to apply to RV128, this version of the document focuses only on RV32 and RV64. |