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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-11 14:31:14 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-11 14:31:14 -0700 |
| commit | 06ec2b2e3698b20b08446ec0bf84df85d8b9debf (patch) | |
| tree | baa01779abb6a43b1e8f976e06d5d368dcc02850 /src | |
| parent | 1317718847de08fc74ca25e1c01b54cdee0d86d1 (diff) | |
| download | riscv-isa-manual-06ec2b2e3698b20b08446ec0bf84df85d8b9debf.zip riscv-isa-manual-06ec2b2e3698b20b08446ec0bf84df85d8b9debf.tar.gz riscv-isa-manual-06ec2b2e3698b20b08446ec0bf84df85d8b9debf.tar.bz2 | |
Interrupt conditions are also evaluated on falling edges
Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 3 | ||||
| -rw-r--r-- | src/supervisor.tex | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex index c3d51ea..c231534 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1385,7 +1385,8 @@ privilege than M-mode; {\tt mideleg}. These conditions for an interrupt trap to occur must be evaluated in a bounded -amount of time from when an interrupt becomes pending in {\tt mip}, and must +amount of time from when an interrupt becomes, or ceases to be, +pending in {\tt mip}, and must also be evaluated immediately following the execution of an {\em x}\/RET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including {\tt mip}, {\tt mie}, {\tt mstatus}, diff --git a/src/supervisor.tex b/src/supervisor.tex index 4680bae..a192360 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -376,7 +376,8 @@ privilege than S-mode; and (b)~bit~\textit{i} is set in both {\tt sip} and {\tt sie}. These conditions for an interrupt trap to occur must be evaluated in a bounded -amount of time from when an interrupt becomes pending in {\tt sip}, and must +amount of time from when an interrupt becomes, or ceases to be, +pending in {\tt sip}, and must also be evaluated immediately following the execution of an SRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including {\tt sip}, {\tt sie} and {\tt sstatus}). |