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| author | Bill Traynor <wmat@riscv.org> | 2023-03-20 11:02:17 -0400 |
|---|---|---|
| committer | Bill Traynor <wmat@riscv.org> | 2023-03-20 11:02:17 -0400 |
| commit | 6df80fc2170219e94f54de4063f39bcb806870dd (patch) | |
| tree | a16b21d060160da93524fbfc79b32c1e10bb6a83 /src | |
| parent | 49a32dd0eb8d5907ee33cbb369a70856052cc8a1 (diff) | |
| download | riscv-isa-manual-6df80fc2170219e94f54de4063f39bcb806870dd.zip riscv-isa-manual-6df80fc2170219e94f54de4063f39bcb806870dd.tar.gz riscv-isa-manual-6df80fc2170219e94f54de4063f39bcb806870dd.tar.bz2 | |
Smrnmi: clarify NMIE only affects M-mode synchronous exception behavior
Manually applying change #993 to clarify NMIE only affects M-mode
synchronous exception behavior.
Diffstat (limited to 'src')
| -rw-r--r-- | src/rnmi.adoc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/rnmi.adoc b/src/rnmi.adoc index 406f214..16672f4 100644 --- a/src/rnmi.adoc +++ b/src/rnmi.adoc @@ -146,10 +146,7 @@ The RNMI handler can resume original execution using the new MNRET instruction, which restores the PC from `mnepc`, the privilege mode from `mnstatus`, and also sets `mnstatus`.NMIE, which re-enables interrupts. -If the hart encounters an exception while the `mnstatus`.NMIE bit is -clear, the actions taken are the same as if the exception had occurred -while `mnstatus`.NMIE were set, except that the program counter is set -to the RNMI exception trap handler address (rather than the address +If the hart encounters an exception while executing in M-mode with the `mnstatus`.NMIE bit clear, the actions taken are the same as if the exception had occurredwhile `mnstatus`.NMIE were set, except that the program counter is set to the RNMI exception trap handler address (rather than the address specified by `mtvec`). [NOTE] |