Updates to the memory consistency model spec

This giant patch is the result of months of work from a lot of
different people in the memory model TG.

1 files changed, 23 insertions, 0 deletions

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+\chapter{``Ztso'' Standard Extension for Total Store Ordering, v0.1}
+\label{sec:ztso}
+
+This chapter defines the ``Ztso'' extension for the RISC-V Total Store Ordering (RVTSO) memory consistency model.
+RVTSO is defined as a delta from RVWMO, which is defined in Chapter~\ref{sec:rvwmo}.
+
+\begin{commentary}
+  The Ztso extension is meant to facilitate the porting of code originally written for the x86 or SPARC architectures, both of which use TSO by default, as well as to support implementations which inherently implement RVTSO.
+  However, in spite of the fact that ``Ztso'' adds no new instructions to the ISA, code written assuming RVTSO will not run correctly on implementations not supporting Ztso.
+  Binaries compiled to run only under Ztso should indicate as such via a flag in the binary, so that platforms which do not implement Ztso can simply refuse to run them.
+\end{commentary}
+
+RVTSO requires the following adjustments to RVWMO:
+
+\begin{itemize}
+  \item All load operations behave as if they have an acquire-RCpc annotation
+  \item All store operations behave as if they have a release-RCpc annotation.
+  \item All AMOs behave as if they have both acquire-RCsc and release-RCsc annotations.
+\end{itemize}
+
+These rules render all PPO rules except \ref{ppo:fence}--\ref{ppo:rcsc} redundant.
+They also make redundant any non-I/O fences that do not have both PW and SR set.
+Finally, they also imply that no instruction will be reordered past an AMO in either direction.