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| author | Andrew Waterman <andrew@sifive.com> | 2021-05-17 17:23:37 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-02 16:46:30 -0700 |
| commit | 5e5e07f21b57f6b224a4c156639812673523c48b (patch) | |
| tree | 4bf2e51f6c21b2de20ca07f48990e13506f36b75 /src/zfinx.tex | |
| parent | 7579a15512e0c770efa28faf175f67fb03f9c5c3 (diff) | |
| download | riscv-isa-manual-5e5e07f21b57f6b224a4c156639812673523c48b.zip riscv-isa-manual-5e5e07f21b57f6b224a4c156639812673523c48b.tar.gz riscv-isa-manual-5e5e07f21b57f6b224a4c156639812673523c48b.tar.bz2 | |
Update src/zfinx.tex
Co-authored-by: Paul Donahue <48959409+pdonahue-ventana@users.noreply.github.com>
Diffstat (limited to 'src/zfinx.tex')
| -rw-r--r-- | src/zfinx.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/zfinx.tex b/src/zfinx.tex index d731e36..1dd65bf 100644 --- a/src/zfinx.tex +++ b/src/zfinx.tex @@ -112,7 +112,7 @@ Register moves need only a single FSGNJ.D instruction, however. \end{commentary} \begin{commentary} -In future, an RV64Zqinx quad-precision extension could be defined analogously +In the future, an RV64Zqinx quad-precision extension could be defined analogously to RV32Zdinx. An RV32Zqinx extension could also be defined but would require quad-register groups. |