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author | Andrew Waterman <andrew@sifive.com> | 2022-08-19 00:47:01 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2022-08-19 00:48:22 -0700 |
commit | 69c1f73d73c2cd3f369eae6b1ab2061509b3e2c7 (patch) | |
tree | f89fbc123e2217d17ffd9a37e6b3e7468e1aa337 /src/zfb.tex | |
parent | 110617039d2c1c1f30959772c5e6d3563844fa2a (diff) | |
download | riscv-isa-manual-69c1f73d73c2cd3f369eae6b1ab2061509b3e2c7.zip riscv-isa-manual-69c1f73d73c2cd3f369eae6b1ab2061509b3e2c7.tar.gz riscv-isa-manual-69c1f73d73c2cd3f369eae6b1ab2061509b3e2c7.tar.bz2 |
Zfb also contains FROUND[.NX]
Diffstat (limited to 'src/zfb.tex')
-rw-r--r-- | src/zfb.tex | 39 |
1 files changed, 37 insertions, 2 deletions
diff --git a/src/zfb.tex b/src/zfb.tex index a765f8e..2d152ed 100644 --- a/src/zfb.tex +++ b/src/zfb.tex @@ -3,8 +3,8 @@ Instructions, Version 0.1} \label{chap:zfb} This chapter describes the Zfb standard extension, which adds instructions for -quiet floating-point comparisons and for the IEEE 754-2019 minimum and maximum -operations. +quiet floating-point comparisons, IEEE 754-2019 minimum and maximum +operations, and round-to-integer operations. For RV32D, the Zfb extension also adds instructions to transfer double-precision floating-point values to and from integer registers, and for RV64Q, it adds analogous instructions for quad-precision floating-point @@ -34,6 +34,41 @@ These instructions implement the IEEE 754-2019 minimum and maximum operations. \end{commentary} +\section{Round-to-Integer Instructions} + +The FROUND.S instruction rounds the single-precision floating-point number in +floating-point register {\em rs1} to an integer, according to the rounding +mode specified in the instruction's {\em rm} field. +It then writes that integer, represented as a single-precision floating-point +number, to floating-point register {\em rd}. +Zero and infinite inputs are copied to {\em rd} unmodified. +Signaling NaN inputs cause the invalid operation exception flag to be set; no +other exception flags are set. +FROUND.S is encoded like FCVT.S.D, but with {\em rs2}=4. + +The FROUND.NX.S instruction is defined similarly, but it also sets the inexact +exception flag if the input differs from the rounded result and is not NaN. +FROUND.NX.S is encoded like FCVT.S.D, but with {\em rs2}=5. + +If the D extension is implemented, FROUND.D and FROUND.NX.D instructions are +analogously defined to operate on double-precision numbers. +They are encoded like FCVT.D.S, but with {\em rs2}=4 and 5, respectively, + +If the Zfh extension is implemented, FROUND.H and FROUND.NX.H instructions are +analogously defined to operate on half-precision numbers. +They are encoded like FCVT.H.S, but with {\em rs2}=4 and 5, respectively, + +If the Q extension is implemented, FROUND.Q and FROUND.NX.Q instructions are +analogously defined to operate on quad-precision numbers. +They are encoded like FCVT.Q.S, but with {\em rs2}=4 and 5, respectively, + +\begin{commentary} +The FROUND.NX.{\em fmt} instructions implement the IEEE 754-2019 +roundToIntegralExact operation, and the FROUND.{\em fmt} instructions +implement the other operations in the roundToIntegral family. +\end{commentary} + + \section{Comparison Instructions} The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S |