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| author | wmat <wmat@riscv.org> | 2024-02-22 10:49:32 -0500 |
|---|---|---|
| committer | wmat <wmat@riscv.org> | 2024-02-22 10:49:32 -0500 |
| commit | c6c03aab9ef300cdec5c45c6faeddf5d74d2c5ec (patch) | |
| tree | 62c8faef9b974e25fdf57344ea4559aec3a3ef1b /src/zc.adoc | |
| parent | 146c3738a7a2866a6d8143dfbc2764ac8e7117f3 (diff) | |
| download | riscv-isa-manual-c6c03aab9ef300cdec5c45c6faeddf5d74d2c5ec.zip riscv-isa-manual-c6c03aab9ef300cdec5c45c6faeddf5d74d2c5ec.tar.gz riscv-isa-manual-c6c03aab9ef300cdec5c45c6faeddf5d74d2c5ec.tar.bz2 | |
Fix formatting
Fixing formatting of rs1' text.
Diffstat (limited to 'src/zc.adoc')
| -rw-r--r-- | src/zc.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/zc.adoc b/src/zc.adoc index 28fc904..b407374 100644 --- a/src/zc.adoc +++ b/src/zc.adoc @@ -365,11 +365,11 @@ The immediate offset is formed as follows: Description: -This instruction loads a byte from the memory address formed by adding `__rs1__` to the zero extended immediate _uimm_. The resulting byte is zero extended to XLEN bits and is written to _rd'_. +This instruction loads a byte from the memory address formed by adding _rs1'_ to the zero extended immediate _uimm_. The resulting byte is zero extended to XLEN bits and is written to _rd'_. [NOTE] ==== -`__rd__` and `__rs1__` are from the standard 8-register set x8-x15. +_rd'_ and _rs1'_ are from the standard 8-register set x8-x15. ==== Prerequisites: |