aboutsummaryrefslogtreecommitdiff
path: root/src/v.tex
diff options
context:
space:
mode:
authorrespasa <31482583+respasa@users.noreply.github.com>2017-08-31 16:16:14 +0200
committerGitHub <noreply@github.com>2017-08-31 16:16:14 +0200
commit54192cd217544dcde638eed803c41d74773bc756 (patch)
tree107201ca3261e7e2d86f8ac53a48e193935431ad /src/v.tex
parenta62e76cb16eb508199f74632eb8bf263739f25a3 (diff)
downloadriscv-isa-manual-54192cd217544dcde638eed803c41d74773bc756.zip
riscv-isa-manual-54192cd217544dcde638eed803c41d74773bc756.tar.gz
riscv-isa-manual-54192cd217544dcde638eed803c41d74773bc756.tar.bz2
Update v.tex
Diffstat (limited to 'src/v.tex')
-rw-r--r--src/v.tex4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/v.tex b/src/v.tex
index 7bd62d7..2d24696 100644
--- a/src/v.tex
+++ b/src/v.tex
@@ -389,6 +389,10 @@ The number of vector predicate registers supported in
predicate registers, but it is not clear these would be used
frequently enough to warrant increased the architectural cost for
all implementations.
+
+ roger: we should force the minimum number of vp registers to 2, so that vp0
+ and vp1 are always available to the compiler. This would work nicer with
+ the encoding that has a bit that allows selecting vp0 or vp1.
\end{discussion}
When {\tt vnp} is 0, any instruction that reads a vector predicate