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author | respasa <31482583+respasa@users.noreply.github.com> | 2017-08-31 16:16:14 +0200 |
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committer | GitHub <noreply@github.com> | 2017-08-31 16:16:14 +0200 |
commit | 54192cd217544dcde638eed803c41d74773bc756 (patch) | |
tree | 107201ca3261e7e2d86f8ac53a48e193935431ad /src/v.tex | |
parent | a62e76cb16eb508199f74632eb8bf263739f25a3 (diff) | |
download | riscv-isa-manual-54192cd217544dcde638eed803c41d74773bc756.zip riscv-isa-manual-54192cd217544dcde638eed803c41d74773bc756.tar.gz riscv-isa-manual-54192cd217544dcde638eed803c41d74773bc756.tar.bz2 |
Update v.tex
Diffstat (limited to 'src/v.tex')
-rw-r--r-- | src/v.tex | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -389,6 +389,10 @@ The number of vector predicate registers supported in predicate registers, but it is not clear these would be used frequently enough to warrant increased the architectural cost for all implementations. + + roger: we should force the minimum number of vp registers to 2, so that vp0 + and vp1 are always available to the compiler. This would work nicer with + the encoding that has a bit that allows selecting vp0 or vp1. \end{discussion} When {\tt vnp} is 0, any instruction that reads a vector predicate |