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authorPaul Wise <pabs3@bonedaddy.net>2017-06-12 10:37:19 +0800
committerAndrew Waterman <aswaterman@gmail.com>2017-06-12 10:58:39 -0700
commit4cebade96f35ba3ba22cca6eaaf330b0a8e4e584 (patch)
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parentd374bfa02da395270ebec5c8eec14fed8e09eff6 (diff)
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Fix word case, typos and word choice
Suggested-by: codespell Suggested-by: spellintian
Diffstat (limited to 'src/v.tex')
-rw-r--r--src/v.tex2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/v.tex b/src/v.tex
index 4d4e2d1..ec14899 100644
--- a/src/v.tex
+++ b/src/v.tex
@@ -438,7 +438,7 @@ no predicate registers are allocated.
holding 5-bit vector register numbers for each supported
type. Fields must either contain 0 indicating no vector registers
are allocated for that type, or a vector register number greater
- than all to the right. All vector register numbers inbetween two
+ than all to the right. All vector register numbers between two
non-zero fields are allocated to the type with the higher vector
register number. }
\label{fig:vdcfg}