Add non-normative text about VIPT caches not being exposed

1 files changed, 9 insertions, 0 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index af0845d..8b6f1a9 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -1203,6 +1203,15 @@ to implement software TLB refills using a machine-mode trap handler as
 an extension to M-mode.
 \end{commentary}
 
+\begin{commentary}
+Some ISAs architecturally expose \emph{virtually indexed, physically tagged}
+caches, in that accesses to the same physical address via different virtual
+addresses might not be coherent unless the virtual addresses lie within the
+same cache set.
+Implicitly, this specification does not permit such behavior to be
+architecturally exposed.
+\end{commentary}
+
 \subsection{Addressing and Memory Protection}
 \label{sec:translation}