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author | Andrew Waterman <andrew@sifive.com> | 2021-06-26 19:01:50 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2021-06-26 19:01:50 -0700 |
commit | e71fc90409416e20aa7dc5840f351551ca0e5750 (patch) | |
tree | 90c905c5784bfa093ca108b103be37f251445e70 /src/supervisor.tex | |
parent | 98f3349c64a134068f462272f8d85f71bbe42b61 (diff) | |
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Add non-normative text about VIPT caches not being exposed
Diffstat (limited to 'src/supervisor.tex')
-rw-r--r-- | src/supervisor.tex | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index af0845d..8b6f1a9 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1203,6 +1203,15 @@ to implement software TLB refills using a machine-mode trap handler as an extension to M-mode. \end{commentary} +\begin{commentary} +Some ISAs architecturally expose \emph{virtually indexed, physically tagged} +caches, in that accesses to the same physical address via different virtual +addresses might not be coherent unless the virtual addresses lie within the +same cache set. +Implicitly, this specification does not permit such behavior to be +architecturally exposed. +\end{commentary} + \subsection{Addressing and Memory Protection} \label{sec:translation} |