minor grammatical and stylistic changes

1 files changed, 6 insertions, 6 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index ec80f20..e12efbe 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -1929,7 +1929,7 @@ Chapter~\ref{svnapot}.  If Svnapot is not implemented, bit 63 remains
 reserved and must be zeroed by software for forward compatibility,
 or else a page-fault exception is raised.
 Bits 62--61 are reserved for use by the Svpbmt extension in
-Chapter~\ref{svpbmt}.  If Svpbmt is not implemented, bits 62--61
+Chapter~\ref{svpbmt}.  If Svpbmt is not implemented, bits 62--61 remain
 reserved and must be zeroed by software for forward compatibility,
 or else a page-fault exception is raised.
 Bits 60--54 are reserved
@@ -2309,9 +2309,9 @@ algorithm in Section~\ref{sv32algorithm}, except that:
   of a single TLB entry covering the entire NAPOT region.  It is also designed
   to be consistent with implementations that support NAPOT PTEs by splitting
   the NAPOT region into TLB entries covering any smaller power-of-two region
-  sizes.  For example, a 64KiB NAPOT PTE might trigger the creation of 16
-  standard 4KiB TLB entries, all with contents generated from the NAPOT PTE
-  (even if the PTEs for the other 4KiB regions have different contents).
+  sizes.  For example, a 64~KiB NAPOT PTE might trigger the creation of 16
+  standard 4~KiB TLB entries, all with contents generated from the NAPOT PTE
+  (even if the PTEs for the other 4~KiB regions have different contents).
 
   In typical usage scenarios, NAPOT PTEs in the same region will have the same
   attributes, same PPNs, and same values for bits 5--0.  RSW remains reserved
@@ -2320,7 +2320,7 @@ algorithm in Section~\ref{sv32algorithm}, except that:
   inconsistencies between NAPOT PTEs and other NAPOT or non-NAPOT PTEs that
   overlap the same address range.  If an update needs to be made, the OS
   generally should first mark all of the PTEs invalid, then issue SFENCE.VMA
-  instruction(s) covering all 4KiB regions within the range (either via a
+  instruction(s) covering all 4~KiB regions within the range (either via a
   single SFENCE.VMA with {\em rs1}={\tt x0}, or with multiple SFENCE.VMA
   instructions with {\em rs1}$\neq${\tt x0}), then update the PTE(s), as
   described in Section~\ref{sec:sfence.vma}, unless any inconsistencies are
@@ -2378,7 +2378,7 @@ algorithm in Section~\ref{sv32algorithm}, except that:
   of $pte.ppn[i]$) may be repurposed for other uses in the future.
 
   However, in case finer-grained intermediate page size support proves not to
-  be useful, we have chosen to standardize only 64KiB support as a first step.
+  be useful, we have chosen to standardize only 64~KiB support as a first step.
 \end{commentary}
 
 \chapter{``Svpbmt'' Standard Extension for Page-Based Memory Types, Version 1.0}