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| author | Andrew Waterman <andrew@sifive.com> | 2021-11-28 20:38:18 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-11-28 22:48:42 -0800 |
| commit | 71e29fd30cdfa26fc9a630260523ff18b55fd43a (patch) | |
| tree | 187af0d34d7f16065a41c45d163e50d044a85452 /src/supervisor.tex | |
| parent | 5500f6ced75a376495570b3993431c0c49d2f630 (diff) | |
| download | riscv-isa-manual-71e29fd30cdfa26fc9a630260523ff18b55fd43a.zip riscv-isa-manual-71e29fd30cdfa26fc9a630260523ff18b55fd43a.tar.gz riscv-isa-manual-71e29fd30cdfa26fc9a630260523ff18b55fd43a.tar.bz2 | |
Split RV32 [v]sstatus figures into two rows
No functional change intended.
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 46 |
1 files changed, 29 insertions, 17 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 76cadf1..45fa5bd 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -46,17 +46,31 @@ register keeps track of the processor's current operating state. {\footnotesize \begin{center} \setlength{\tabcolsep}{4pt} -\scalebox{0.95}{ -\begin{tabular}{cWcccccWccccWcc} +\begin{tabular}{cEcccc} \\ \instbit{31} & \instbitrange{30}{20} & \instbit{19} & \instbit{18} & \instbit{17} & + \\ +\hline +\multicolumn{1}{|c|}{SD} & +\multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{c|}{MXR} & +\multicolumn{1}{c|}{SUM} & +\multicolumn{1}{c|}{\wpri} & + \\ +\hline +1 & 11 & 1 & 1 & 1 & \\ +\end{tabular} +\begin{tabular}{cWWWWccccWcc} +\\ +& \instbitrange{16}{15} & \instbitrange{14}{13} & -\instbitrange{12}{9} & +\instbitrange{12}{11} & +\instbitrange{10}{9} & \instbit{8} & \instbit{7} & \instbit{6} & @@ -65,25 +79,21 @@ register keeps track of the processor's current operating state. \instbit{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{SD} & -\multicolumn{1}{c|}{\wpri} & -\multicolumn{1}{c|}{MXR} & -\multicolumn{1}{c|}{SUM} & -\multicolumn{1}{c|}{\wpri} & -\multicolumn{1}{c|}{XS[1:0]} & + & +\multicolumn{1}{|c|}{XS[1:0]} & \multicolumn{1}{c|}{FS[1:0]} & \multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SPP} & \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{UBE} & \multicolumn{1}{c|}{SPIE} & \multicolumn{1}{c|}{\wpri} & -\multicolumn{1}{c|}{SIE} & -\multicolumn{1}{c|}{\wpri} -\\ +\multicolumn{1}{c|}{SIE} & +\multicolumn{1}{c|}{\wpri} \\ \hline -1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\ -\end{tabular}} + & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\ +\end{tabular} \end{center} } \vspace{-0.1in} @@ -117,12 +127,13 @@ register keeps track of the processor's current operating state. \hline 1 & 29 & 2 & 12 & 1 & 1 & 1 & \\ \end{tabular} -\begin{tabular}{cWWFccccWcc} +\begin{tabular}{cWWWWccccWcc} \\ & \instbitrange{16}{15} & \instbitrange{14}{13} & -\instbitrange{12}{9} & +\instbitrange{12}{11} & +\instbitrange{10}{9} & \instbit{8} & \instbit{7} & \instbit{6} & @@ -135,6 +146,7 @@ register keeps track of the processor's current operating state. \multicolumn{1}{|c|}{XS[1:0]} & \multicolumn{1}{c|}{FS[1:0]} & \multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{SPP} & \multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{UBE} & @@ -143,7 +155,7 @@ register keeps track of the processor's current operating state. \multicolumn{1}{c|}{SIE} & \multicolumn{1}{c|}{\wpri} \\ \hline - & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\ + & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\ \end{tabular} \end{center} } |