Add the Svinval standard extension

1 files changed, 190 insertions, 0 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index f3b7a3b..ec80f20 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -2466,3 +2466,193 @@ Otherwise, the PMAs serve as the intermediate attributes.  Second, if
 the intermediate attributes to produce the final set of attributes used by
 accesses to the page in question.  Otherwise, the intermediate attributes are
 used as the final set of attributes.
+
+\chapter{``Svinval'' Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0}
+\label{svinval}
+
+The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA
+instructions into finer-grained invalidation and ordering operations that can
+be more efficiently batched or pipelined on certain classes of high-performance
+implementation.
+
+\vspace{-0.2in}
+\begin{center}
+\begin{tabular}{O@{}R@{}R@{}F@{}R@{}S}
+\\
+\instbitrange{31}{25} &
+\instbitrange{24}{20} &
+\instbitrange{19}{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{7} &
+\instbitrange{6}{0} \\
+\hline
+\multicolumn{1}{|c|}{funct7} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{opcode} \\
+\hline
+7 & 5 & 5 & 3 & 5 & 7 \\
+SINVAL.VMA & asid & vaddr & PRIV & 0 & SYSTEM \\
+\end{tabular}
+\end{center}
+
+The SINVAL.VMA instruction invalidates any address-translation cache entries
+that an SFENCE.VMA instruction with the same values of {\em rs1} and {\em rs2}
+would invalidate.  However, unlike SFENCE.VMA, SINVAL.VMA instructions are only
+ordered with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR
+instructions as defined below.
+
+\vspace{-0.2in}
+\begin{center}
+\begin{tabular}{O@{}R@{}R@{}F@{}R@{}S}
+\\
+\instbitrange{31}{25} &
+\instbitrange{24}{20} &
+\instbitrange{19}{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{7} &
+\instbitrange{6}{0} \\
+\hline
+\multicolumn{1}{|c|}{funct7} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{opcode} \\
+\hline
+7 & 5 & 5 & 3 & 5 & 7 \\
+SFENCE.W.INVAL & 0 & 0 & PRIV & 0 & SYSTEM \\
+\end{tabular}
+\end{center}
+
+\vspace{-0.2in}
+\begin{center}
+\begin{tabular}{O@{}R@{}R@{}F@{}R@{}S}
+\\
+\instbitrange{31}{25} &
+\instbitrange{24}{20} &
+\instbitrange{19}{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{7} &
+\instbitrange{6}{0} \\
+\hline
+\multicolumn{1}{|c|}{funct7} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{opcode} \\
+\hline
+7 & 5 & 5 & 3 & 5 & 7 \\
+SFENCE.INVAL.IR & 1 & 0 & PRIV & 0 & SYSTEM \\
+\end{tabular}
+\end{center}
+
+The SFENCE.W.INVAL instruction guarantees that any previous stores already
+visible to the current RISC-V hart are ordered before subsequent SINVAL.VMA
+instructions executed by the same hart.  The SFENCE.INVAL.IR instruction
+guarantees that any previous SINVAL.VMA instructions executed by the current hart
+are ordered before subsequent implicit references by that hart to the
+memory-management data structures.
+
+When executed in order (but not necessarily consecutively) by a single hart, the
+sequence SFENCE.W.INVAL, SINVAL.VMA, and SFENCE.INVAL.IR has the same effect as
+a hypothetical SFENCE.VMA instruction in which:
+\begin{itemize}
+  \item the values of {\em rs1} and {\em rs2} for the SFENCE.VMA are the same
+    as those used in the SINVAL.VMA,
+  \item reads and writes prior to the SFENCE.W.INVAL are considered to be those
+    prior to the SFENCE.VMA, and
+  \item reads and writes following the SFENCE.INVAL.IR are considered to be
+    those subsequent to the SFENCE.VMA.
+\end{itemize}
+
+\vspace{-0.2in}
+\begin{center}
+\begin{tabular}{O@{}R@{}R@{}F@{}R@{}S}
+\\
+\instbitrange{31}{25} &
+\instbitrange{24}{20} &
+\instbitrange{19}{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{7} &
+\instbitrange{6}{0} \\
+\hline
+\multicolumn{1}{|c|}{funct7} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{opcode} \\
+\hline
+7 & 5 & 5 & 3 & 5 & 7 \\
+HINVAL.VVMA & asid & vaddr & PRIV & 0 & SYSTEM \\
+\end{tabular}
+\end{center}
+
+\vspace{-0.2in}
+\begin{center}
+\begin{tabular}{O@{}R@{}R@{}F@{}R@{}S}
+\\
+\instbitrange{31}{25} &
+\instbitrange{24}{20} &
+\instbitrange{19}{15} &
+\instbitrange{14}{12} &
+\instbitrange{11}{7} &
+\instbitrange{6}{0} \\
+\hline
+\multicolumn{1}{|c|}{funct7} &
+\multicolumn{1}{c|}{rs2} &
+\multicolumn{1}{c|}{rs1} &
+\multicolumn{1}{c|}{funct3} &
+\multicolumn{1}{c|}{rd} &
+\multicolumn{1}{c|}{opcode} \\
+\hline
+7 & 5 & 5 & 3 & 5 & 7 \\
+HINVAL.GVMA & vmid & gaddr & PRIV & 0 & SYSTEM \\
+\end{tabular}
+\end{center}
+
+If the hypervisor extension is enabled, the Svinval extension also provides two
+additional instructions: HINVAL.VVMA and HINVAL.GVMA.  These have the same
+semantics as SINVAL.VMA, except that they combine with SFENCE.W.INVAL and
+SFENCE.INVAL.IR to replace HFENCE.VVMA and HFENCE.GVMA, respectively, instead
+of SFENCE.VMA.  In addition, HINVAL.GVMA uses VMIDs instead of ASIDs.
+
+SINVAL.VMA, HINVAL.VVMA, and HINVAL.GVMA require the same permissions and raise
+the same exceptions as SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA, respectively.
+In particular, an attempt to execute SINVAL.VMA when {\tt mstatus}.TVM=1 while
+executing in S-mode or HS-mode will raise an illegal instruction exception, and
+an attempt to execute SINVAL.VMA when {\tt hstatus}.VTVM=1 while executing in
+VS-mode raises a virtual instruction exception.  Likewise, an attempt to
+execute HINVAL.GVMA in HS-mode when {\tt mstatus}.TVM=1 raises an illegal
+instruction exception.  An attempt to execute HINVAL.VVMA or HINVAL.GVMA when
+V=1 raises a virtual instruction exception, and an attempt to execute any of
+the above in U-mode raises an illegal instruction exception.
+
+\begin{commentary}
+  SFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be trapped when
+  {\tt mstatus}.TVM=1 or when {\tt hstatus}.VTVM=1, as they only have ordering
+  effects but no visible side effects.  Trapping of the SINVAL.VMA instruction
+  is sufficient to enable emulation of the intended overall TLB maintenance
+  functionality.
+
+  In typical usage, software will invalidate a range of virtual addresses in
+  the address-translation caches by executing an SFENCE.W.INVAL instruction,
+  executing a series of SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions to
+  the addresses (and optionally ASIDs or VMIDs) in question, and then executing
+  an SFENCE.INVAL.IR instruction.
+
+  High-performance implementations will be able to pipeline the
+  address-translation cache invalidation operations, and will defer any
+  pipeline stalls or other memory ordering enforcement until an SFENCE.W.INVAL,
+  SFENCE.INVAL.IR, SFENCE.VMA, HFENCE.GVMA, or HFENCE.VVMA instruction is
+  executed.
+
+  Simpler implementations may implement SINVAL.VMA, HINVAL.VVMA, and
+  HINVAL.GVMA identically to SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA,
+  respectively, while implementing SFENCE.W.INVAL and SFENCE.INVAL.IR
+  instructions as no-ops.
+\end{commentary}