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| author | Andrew Waterman <andrew@sifive.com> | 2017-07-26 12:33:09 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-07-26 12:33:28 -0700 |
| commit | f5dfba4610dcdfed7afb9c63eb511d77f4defc62 (patch) | |
| tree | cfa810055bed7b0e7cb01b584725652ed0ced3ea /src/supervisor.tex | |
| parent | de333adb7a6e4ca2a773505b5a00b7926b84a642 (diff) | |
| download | riscv-isa-manual-f5dfba4610dcdfed7afb9c63eb511d77f4defc62.zip riscv-isa-manual-f5dfba4610dcdfed7afb9c63eb511d77f4defc62.tar.gz riscv-isa-manual-f5dfba4610dcdfed7afb9c63eb511d77f4defc62.tar.bz2 | |
Fix typo in stvec figure
Closes #95
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 95bf329..b7754b2 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -249,7 +249,7 @@ vector mode (MODE). \instbitrange{XLEN-1}{2} & \instbitrange{1}{0} \\ \hline -\multicolumn{1}{|c|}{BASE[XLEN-1:2] (\wlrl)} & +\multicolumn{1}{|c|}{BASE[XLEN-1:2] (\warl)} & \multicolumn{1}{c|}{MODE (\warl)} \\ \hline XLEN-2 & 2 \\ |