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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-05 17:11:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-05 17:11:35 -0700 |
| commit | f1c620d7608a3b6c7c60d0bb96797e40655e60ee (patch) | |
| tree | 9a47356190ce65bcca9aa34ae53aaa180a305e9b /src/supervisor.tex | |
| parent | 326bec83de23f4d2daf24cfed6b5251748cad632 (diff) | |
| download | riscv-isa-manual-f1c620d7608a3b6c7c60d0bb96797e40655e60ee.zip riscv-isa-manual-f1c620d7608a3b6c7c60d0bb96797e40655e60ee.tar.gz riscv-isa-manual-f1c620d7608a3b6c7c60d0bb96797e40655e60ee.tar.bz2 | |
Attempt to explain SEIP discipline
Closes #53
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 9aa0cdb..6a2d7a5 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -345,7 +345,7 @@ USIP bit in {\tt sip}. User-level software interrupts are disabled when the USIE bit in the {\tt sie} register is clear. If user-level interrupts are not supported, USIP and USIE are hardwired to zero. -All bits besides SSIP and USIP in the {\tt sip} register are read-only. +All bits besides SSIP, USIP, and UEIP in the {\tt sip} register are read-only. A supervisor-level timer interrupt is pending if the STIP bit in the {\tt sip} register is set. Supervisor-level timer interrupts are disabled when the STIE @@ -365,9 +365,23 @@ when the SEIE bit in the {\tt sie} register is clear. The SBI should provide facilities to mask, unmask, and query the cause of external interrupts. A user-level external interrupt is pending if the UEIP bit in the -{\tt sip} register is set. User-level external interrupts are disabled -when the UEIE bit in the {\tt sie} register is clear. If user-level -interrupts are not supported, UEIP and UEIE are hardwired to zero. +{\tt sip} register is set. + +The UEIP field in {\tt sip} is a read-write bit that indicates a user-mode +external interrupt is pending. UEIP may be written by S-mode software to +indicate to S-mode that an external interrupt is pending. Additionally, the +platform-level interrupt controller may generate user-level external +interrupts. When the UEIP bit is read with a CSRRW, CSRRS, or CSRRC +instruction, it appears to contain the logical-OR of the software-writable bit +and the interrupt signal from the interrupt controller. However, when the UEIP +bit is written with a CSRRS or CSRRC instruction, only the software-writable +portion of the UEIP bit affects the new value written to the {\tt sip} CSR. +The user-level interrupt signal from the interrupt controller does {\em not} +participate in a CSRRS or CSRRC read-modify-write sequence. + +User-level external interrupts are disabled when the UEIE bit in the {\tt sie} +register is clear. If the N extension for user-level interrupts is not +implemented, UEIP and UEIE are hardwired to zero. \begin{commentary} The {\tt sip} and {\tt sie} registers are subsets of the {\tt mip} and {\tt |