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| author | Andrew Waterman <andrew@sifive.com> | 2017-09-20 12:34:49 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-09-20 12:34:49 -0700 |
| commit | e2ae148dcca7f725a577ca911059edb337b1ef25 (patch) | |
| tree | 842a9dc6ba6e1e09e616682f25e07d384d984686 /src/supervisor.tex | |
| parent | eff624dea22dd5039636b7e84c692cccc8db5834 (diff) | |
| download | riscv-isa-manual-e2ae148dcca7f725a577ca911059edb337b1ef25.zip riscv-isa-manual-e2ae148dcca7f725a577ca911059edb337b1ef25.tar.gz riscv-isa-manual-e2ae148dcca7f725a577ca911059edb337b1ef25.tar.bz2 | |
Clarify mtval; allow platform to specify when it's written
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index ba8dad8..1032011 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -647,13 +647,15 @@ The {\tt stval} register is an XLEN-bit read-write register formatted as shown in Figure~\ref{stvalreg}. When a trap is taken into S-mode, {\tt stval} is written with exception-specific information to assist software in handling the trap. Otherwise, {\tt stval} is never written by the implementation, though -it may be explicitly written by software. +it may be explicitly written by software. The hardware platform will specify +which exceptions must set {\tt stval} informatively and which may +unconditionally set it to zero. When a hardware breakpoint is triggered, or an instruction-fetch, load, or store address-misaligned, access, or page-fault exception occurs, {\tt stval} -is written with the faulting address. On an illegal instruction trap, {\tt -stval} may be written with the first XLEN or ILEN bits of the faulting +is written with the faulting virtual address. On an illegal instruction trap, +{\tt stval} may be written with the first XLEN or ILEN bits of the faulting instruction as described below. For other exceptions, {\tt stval} is set to zero, but a future standard may redefine {\tt stval}'s setting for other exceptions. @@ -675,10 +677,14 @@ XLEN \\ \label{stvalreg} \end{figure} -For instruction-fetch access faults and page faults on RISC-V systems with -variable-length instructions, {\tt stval} will point to the portion -of the instruction that caused the fault while {\tt sepc} will point -to the beginning of the instruction. +For misaligned loads and stores that cause access or page-fault +exceptions, {\tt stval} will contain the virtual address of the +portion of the access that caused the fault. For +instruction-fetch access or page-fault exceptions on systems +with variable-length instructions, {\tt stval} will contain the +virtual address of the portion of the instruction that caused +the fault while {\tt sepc} will point to the beginning of the +instruction. The {\tt stval} register can optionally also be used to return the faulting instruction bits on an illegal instruction exception ({\tt |