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authorAlexandre Joannou <gameboo@users.noreply.github.com>2018-07-07 02:31:48 +0100
committerAndrew Waterman <aswaterman@gmail.com>2018-07-06 18:31:48 -0700
commitc4be3522f1494024364f9290e3e2df06cd69a9f7 (patch)
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parent7ea3f6755c483cba71eb59d052dc71bea139a5ce (diff)
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Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)
* Help the reader by pointing at TVM and TW in the relevant sections * Mention TSR field in SRET description * Avoid leaking M-mode details in S-mode text. * Added a ref in SFENCE.VMA paragraph (PMP synchronization)
Diffstat (limited to 'src/supervisor.tex')
-rw-r--r--src/supervisor.tex6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex
index f86cca5..ca5502e 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -731,7 +731,8 @@ This register holds the physical page number (PPN) of the root page
table, i.e., its supervisor physical address divided by \wunits{4}{KiB};
an address space identifier (ASID), which facilitates address-translation
fences on a per-address-space basis; and the MODE field, which selects the
-current address-translation scheme.
+current address-translation scheme. Further details on the access to this
+register are described in Section~\ref{virt-control}.
\begin{figure}[h!]
{\footnotesize
@@ -917,7 +918,8 @@ these data structures; however, these implicit references are ordinarily not
ordered with respect to loads and stores in the instruction stream. Executing
an SFENCE.VMA instruction guarantees that any stores in the instruction stream
prior to the SFENCE.VMA are ordered before all implicit references subsequent
-to the SFENCE.VMA.
+to the SFENCE.VMA. Further details on the behaviour of this instruction are
+described in Section~\ref{virt-control} and Section~\ref{pmp-vmem}.
\begin{commentary}
The SFENCE.VMA is used to flush any local hardware caches related to