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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-27 15:14:46 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-27 15:16:08 -0800 |
| commit | c4186e39d7c314f17c05ad56b3120779991d85ea (patch) | |
| tree | 0d846ab04df35fc89ef35c81d3fdbd94d7dbd84b /src/supervisor.tex | |
| parent | c7a81b2be5e210da2134b29aeb8e0fda1893cedd (diff) | |
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Remove upper bound on stvec.MODE=Vectored alignment, like mtvec
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 306ba8f..b47d8fe 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -296,8 +296,7 @@ field, whereas interrupts cause the {\tt pc} to be set to the address in the BASE field plus four times the interrupt cause number. For example, a supervisor-mode timer interrupt (see Table~\ref{scauses}) causes the {\tt pc} to be set to BASE+{\tt 0x14}. -Setting MODE=Vectored may impose an additional alignment constraint on BASE, -requiring up to $4\times$SXLEN-byte alignment. +Setting MODE=Vectored may impose a stricter alignment constraint on BASE. \begin{commentary} When vectored interrupts are enabled, interrupt cause 0, which corresponds to |