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| author | Andrew Waterman <andrew@sifive.com> | 2017-08-15 22:18:43 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-08-15 22:19:11 -0700 |
| commit | b6eea1464ff208d23e16b2f3638f312a7020a72b (patch) | |
| tree | 51cbf23c506438b716c2020b3a8d287ae736dbcc /src/supervisor.tex | |
| parent | 270cc7df84623d37e37f35d8de8e990aeaac65e7 (diff) | |
| download | riscv-isa-manual-b6eea1464ff208d23e16b2f3638f312a7020a72b.zip riscv-isa-manual-b6eea1464ff208d23e16b2f3638f312a7020a72b.tar.gz riscv-isa-manual-b6eea1464ff208d23e16b2f3638f312a7020a72b.tar.bz2 | |
Load address misaligned exceptions *can* occur in S-mode
because of the load-reserved instruction.
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index b7754b2..28de897 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -623,9 +623,9 @@ so is only guaranteed to hold supported exception codes. 0 & 1 & Instruction access fault \\ 0 & 2 & Illegal instruction \\ 0 & 3 & Breakpoint \\ - 0 & 4 & {\em Reserved} \\ + 0 & 4 & Load address misaligned \\ 0 & 5 & Load access fault \\ - 0 & 6 & AMO address misaligned \\ + 0 & 6 & Store/AMO address misaligned \\ 0 & 7 & Store/AMO access fault \\ 0 & 8 & Environment call \\ 0 & 9--11 & {\em Reserved} \\ @@ -649,13 +649,14 @@ written with exception-specific information to assist software in handling the trap. Otherwise, {\tt stval} is never written by the implementation, though it may be explicitly written by software. + When a hardware breakpoint is triggered, or an instruction-fetch, load, or -store access or page-fault exception occurs, or an instruction-fetch or AMO -address-misaligned exception occurs, {\tt stval} is written with the -faulting address. On an illegal instruction trap, {\tt stval} may be -written with the first XLEN or ILEN bits of the faulting instruction as -described below. For other exceptions, {\tt stval} is set to zero, but a -future standard may redefine {\tt stval}'s setting for other exceptions. +store address-misaligned, access, or page-fault exception occurs, {\tt stval} +is written with the faulting address. On an illegal instruction trap, {\tt +stval} may be written with the first XLEN or ILEN bits of the faulting +instruction as described below. For other exceptions, {\tt stval} is set to +zero, but a future standard may redefine {\tt stval}'s setting for other +exceptions. \begin{figure}[h!] {\footnotesize |