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| author | Andrew Waterman <andrew@sifive.com> | 2017-12-06 12:15:49 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-12-06 12:16:05 -0800 |
| commit | b62e649445d1f02dfcc8123f64dce598baceb5ab (patch) | |
| tree | b23196ee7ae4b275ec33dde20c7e3e97e1e350f2 /src/supervisor.tex | |
| parent | de30d5541109e4485de5e07c90f4b1f2adad3ae8 (diff) | |
| download | riscv-isa-manual-b62e649445d1f02dfcc8123f64dce598baceb5ab.zip riscv-isa-manual-b62e649445d1f02dfcc8123f64dce598baceb5ab.tar.gz riscv-isa-manual-b62e649445d1f02dfcc8123f64dce598baceb5ab.tar.bz2 | |
Constrain all harts to use same A/D-bit management scheme
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 3bd0c8b..be8e5d6 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1182,8 +1182,7 @@ Two schemes to manage the A and D bits are permitted: \item When a virtual page is accessed and the A bit is clear, or is written and the D bit is clear, a page-fault exception is raised. \end{itemize} -Standard supervisor software should be written to assume either or both -PTE update schemes may be in effect. +All harts in a system must employ the same PTE-update scheme as each other. \begin{commentary} Mandating that the PTE updates to be exact, atomic, and in program order |