Incorporate Allen's feedback

1 files changed, 6 insertions, 4 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index 26073cc..dfcfa85 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -281,8 +281,9 @@ requiring up to $4\times$XLEN-byte alignment.
 \begin{commentary}
 When vectored interrupts are enabled, interrupt cause 0, which corresponds to
 user-mode software interrupts, are vectored to the same location as
-synchronous exceptions.  This ambiguity does not arise in practice, since
-user-mode software interrupts are either disabled or delegated to user mode.
+synchronous exceptions.  This ambiguity does not arise in practice for
+supervisor software, since user-mode software interrupts are either disabled
+or delegated to user mode.
 \end{commentary}
 
 \subsection{Supervisor Interrupt Registers ({\tt sip} and {\tt sie})}
@@ -561,6 +562,7 @@ Otherwise, {\tt scause} is never written by the implementation, though it may be
 explicitly written by software.
 
 The Interrupt bit in the {\tt scause} register is set if the
+trap was caused by an interrupt. The Exception Code field
 contains a code identifying the last exception.  Table~\ref{scauses}
 lists the possible exception codes for the current supervisor ISAs, in
 descending order of priority.  The Exception Code is an \wlrl\ field,
@@ -895,8 +897,8 @@ writes and the address translation hardware.
 \end{commentary}
 
 \begin{commentary}
-Note the instruction has no effect on the translations of other RISC-V
-threads, which must be notified separately.  One approach is to use 1)
+Note the instruction has no effect on the translations of other harts,
+which must be notified separately.  One approach is to use 1)
 a local data fence to ensure local writes are visible globally, then
 2) an interprocessor interrupt to the other thread, then 3) a local
 SFENCE.VMA in the interrupt handler of the remote thread, and finally