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| author | Andrew Waterman <andrew@sifive.com> | 2017-05-04 22:29:56 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-05-04 22:29:56 -0700 |
| commit | b3d3009fa7f45fbf8b41713f510208caf88a246e (patch) | |
| tree | c56313a14a738f3ccaf4038b14fee6c86fc4bf0b /src/supervisor.tex | |
| parent | 8ca7cc545451f97b8941f19c5ca7fcc05494df40 (diff) | |
| download | riscv-isa-manual-b3d3009fa7f45fbf8b41713f510208caf88a246e.zip riscv-isa-manual-b3d3009fa7f45fbf8b41713f510208caf88a246e.tar.gz riscv-isa-manual-b3d3009fa7f45fbf8b41713f510208caf88a246e.tar.bz2 | |
Reserve D/A/U bits
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 0613c57..099915d 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1107,6 +1107,9 @@ Any level of PTE may be a leaf PTE, so in addition to 4 KiB pages, Sv32 supports 4 MiB {\em megapages}. A megapage must be virtually and physically aligned to a 4 MiB boundary. +For non-leaf PTEs, the D, A, and U bits are reserved for future use and +must be cleared by software for forward compatibility. + \subsection{Virtual Address Translation Process} \label{sv32algorithm} |