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| author | Andrew Waterman <andrew@sifive.com> | 2018-07-06 12:16:12 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-07-06 12:16:12 -0700 |
| commit | b2c306f6310aae65ac52e273dc204550ec776e7e (patch) | |
| tree | 16102583e4f0789ce02ac8334ff91c84fcf9cd84 /src/supervisor.tex | |
| parent | 1e9e18b8dd385102f1832879c3761e1c6d455430 (diff) | |
| download | riscv-isa-manual-b2c306f6310aae65ac52e273dc204550ec776e7e.zip riscv-isa-manual-b2c306f6310aae65ac52e273dc204550ec776e7e.tar.gz riscv-isa-manual-b2c306f6310aae65ac52e273dc204550ec776e7e.tar.bz2 | |
Explain how addressing works when UXLEN < SXLEN
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 15c33e8..f86cca5 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -197,6 +197,11 @@ If UXLEN~$\ne$~SXLEN, instructions executed in the narrower mode must ignore source register operand bits above the configured XLEN, and must sign-extend results to fill the widest supported XLEN in the destination register. +If UXLEN~$<$~SXLEN, user-mode instruction-fetch addresses and load and store +effective addresses are taken modulo $2^{UXLEN}$. For example, when UXLEN=32 +and SXLEN=64, user-mode memory accesses reference the lowest \wunits{4}{GiB} +of the address space. + \subsection{Memory Privilege in {\tt sstatus} Register} \label{sec:sum} |