Add ILEN to simplify descriptions of {m,s}tval CSRs

1 files changed, 16 insertions, 13 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index 8af221d..b3f0307 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -631,13 +631,13 @@ written with exception-specific information to assist software in handling the
 trap.  Otherwise, {\tt stval} is never written by the implementation, though
 it may be explicitly written by software.
 
-When a hardware breakpoint is triggered, or
-an instruction-fetch, load, or store access or page-fault exception occurs,
-or an instruction-fetch or AMO address-misaligned exception occurs,
-{\tt stval} is written with the faulting address.
-For other exceptions, {\tt stval} is
-set to zero, but a future standard may redefine {\tt stval}'s setting for
-other exceptions.
+When a hardware breakpoint is triggered, or an instruction-fetch, load, or
+store access or page-fault exception occurs, or an instruction-fetch or AMO
+address-misaligned exception occurs, {\tt stval} is written with the
+faulting address.  On an illegal instruction trap, {\tt stval} may be
+written with the first XLEN or ILEN bits of the faulting instruction as
+described below.  For other exceptions, {\tt stval} is set to zero, but a
+future standard may redefine {\tt stval}'s setting for other exceptions.
 
 \begin{figure}[h!]
 {\footnotesize
@@ -668,12 +668,15 @@ faulting instruction bits on an illegal instruction exception ({\tt
 If this feature is not provided, then {\tt stval} is set to zero on
 an illegal instruction fault.
 
-If the feature is provided, after an illegal instruction trap, {\tt
-  stval} will contain the entire faulting instruction provided the
-instruction is no longer than XLEN bits.  If the instruction is less
-than XLEN bits long, the upper bits of {\tt stval} are cleared to
-zero. If the instruction is more than XLEN bits long, {\tt stval}
-will contain the first XLEN bits of the instruction.
+If this feature is provided, after an illegal instruction trap, {\tt stval}
+will contain the shortest of:
+\begin{compactitem}
+\item the actual faulting instruction
+\item the first ILEN bits of the faulting instruction
+\item the first XLEN bits of the faulting instruction
+\end{compactitem}
+The value loaded into {\tt stval} is right-justified and all unused upper
+bits are cleared to zero.
 
 {\tt stval} is a \warl\ register that must be able to hold all valid physical
 and virtual addresses and the value 0.  It need not be capable of holding all