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authorAndrew Waterman <andrew@sifive.com>2017-06-12 14:16:49 -0700
committerAndrew Waterman <andrew@sifive.com>2017-06-12 14:16:49 -0700
commit8df1abd8d990297894bf31da40a652a2b12dcc01 (patch)
treec2d1881b6717f58b0502cf7827d969c25dd612b3 /src/supervisor.tex
parent6c38e6fbdd571037a476692be92e77f48c31b87e (diff)
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Clarify access exception type in page-table walk algorithm
Diffstat (limited to 'src/supervisor.tex')
-rw-r--r--src/supervisor.tex5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 7da4cc2..95bf329 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -1198,7 +1198,7 @@ follows:
\item Let $pte$ be the value of the PTE at address
$a+va.vpn[i]\times \textrm{PTESIZE}$. (For Sv32, PTESIZE=4.)
If accessing $pte$ violates a PMA or PMP check, raise an
- access exception.
+ access exception corresponding to the original access type.
\item If $pte.v=0$, or if $pte.r=0$ and $pte.w=1$, stop and raise a page-fault exception.
@@ -1221,7 +1221,8 @@ follows:
\begin{itemize}
\item Set $pte.a$ to 1 and, if the memory access is a store, also set
$pte.d$ to 1.
- \item If this access violates a PMA or PMP check, raise an access exception.
+ \item If this access violates a PMA or PMP check, raise an access exception
+ corresponding to the original access type.
\item This update and the loading of $pte$ in step 2 must be atomic; in
particular, no intervening store to the PTE may be perceived to have
occurred in-between.