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| author | Krste Asanovic <krste@sifive.com> | 2017-05-06 22:05:44 +0100 |
|---|---|---|
| committer | Krste Asanovic <krste@sifive.com> | 2017-05-06 22:05:44 +0100 |
| commit | 6a1e92cc59da2cd79810f67e628f9f023f400df4 (patch) | |
| tree | 84422735331f200ddb11d9424b54766f423dd68f /src/supervisor.tex | |
| parent | 68595ce60ef488db277f774349a24df1fa6d7d40 (diff) | |
| download | riscv-isa-manual-6a1e92cc59da2cd79810f67e628f9f023f400df4.zip riscv-isa-manual-6a1e92cc59da2cd79810f67e628f9f023f400df4.tar.gz riscv-isa-manual-6a1e92cc59da2cd79810f67e628f9f023f400df4.tar.bz2 | |
Fixed some lingering references to bad address register.
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 7a608f2..645ad18 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -590,7 +590,7 @@ so is only guaranteed to hold supported exception codes. \label{scauses} \end{table*} -\subsection{Supervisor Bad Address ({\tt stval}) Register} +\subsection{Supervisor Trap Value ({\tt stval}) Register} The {\tt stval} register is an XLEN-bit read-write register formatted as shown in Figure~\ref{stvalreg}. When a trap is taken into S-mode, {\tt stval} is @@ -619,7 +619,7 @@ XLEN \\ \end{center} } \vspace{-0.1in} -\caption{Supervisor bad address register.} +\caption{Supervisor Trap Value register.} \label{stvalreg} \end{figure} |