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| author | Andrew Waterman <andrew@sifive.com> | 2018-11-05 11:52:12 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-11-05 11:52:35 -0800 |
| commit | 4420a191d2b4116a6f637b654010a8186d2af136 (patch) | |
| tree | 59a7798176c378893af4dae98eb1ffe8b32b226c /src/supervisor.tex | |
| parent | 0c576ca013c6df0713057063dc915603f1b49292 (diff) | |
| download | riscv-isa-manual-4420a191d2b4116a6f637b654010a8186d2af136.zip riscv-isa-manual-4420a191d2b4116a6f637b654010a8186d2af136.tar.gz riscv-isa-manual-4420a191d2b4116a6f637b654010a8186d2af136.tar.bz2 | |
Fix spelling
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index e1fc486..68e8873 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -919,7 +919,7 @@ these data structures; however, these implicit references are ordinarily not ordered with respect to loads and stores in the instruction stream. Executing an SFENCE.VMA instruction guarantees that any stores in the instruction stream prior to the SFENCE.VMA are ordered before all implicit references subsequent -to the SFENCE.VMA. Further details on the behaviour of this instruction are +to the SFENCE.VMA. Further details on the behavior of this instruction are described in Section~\ref{virt-control} and Section~\ref{pmp-vmem}. \begin{commentary} |