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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-09-24 00:30:50 -0700 |
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| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-09-24 00:30:50 -0700 |
| commit | 3666bb19913ddbc893f9cfc74da8af6f6ae046be (patch) | |
| tree | 3abf72a7095db9c2aa31aa0378626f0bc2d425d9 /src/supervisor.tex | |
| parent | 4c6ee856fcd8576d582a14b55fdab4e72483a804 (diff) | |
| download | riscv-isa-manual-3666bb19913ddbc893f9cfc74da8af6f6ae046be.zip riscv-isa-manual-3666bb19913ddbc893f9cfc74da8af6f6ae046be.tar.gz riscv-isa-manual-3666bb19913ddbc893f9cfc74da8af6f6ae046be.tar.bz2 | |
Improving lanuage.
Closed #215
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index fa9aaa0..6585bbd 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -558,9 +558,9 @@ addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt sepc}. When a trap is taken into S-mode, {\tt sepc} is written with the -virtual address of the instruction that encountered the exception or -was interrupted. Otherwise, {\tt sepc} is never written by the -implementation, though it may be explicitly written by software. +virtual address of the instruction that was interrupted or that +encountered the exception. Otherwise, {\tt sepc} is never written by +the implementation, though it may be explicitly written by software. \begin{figure}[h!] {\footnotesize |