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| author | Premjith <premjith@cdac.in> | 2018-04-17 16:15:09 +0530 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2018-04-17 11:00:01 -0700 |
| commit | 297d2021fa86e9217f412f8c6c7e436f07911094 (patch) | |
| tree | b4a986ef224e3cca8d923a9de6e5e2c9dc63307a /src/supervisor.tex | |
| parent | 593d641943ee9d0d503a0aac093a63904a42b4bf (diff) | |
| download | riscv-isa-manual-297d2021fa86e9217f412f8c6c7e436f07911094.zip riscv-isa-manual-297d2021fa86e9217f412f8c6c7e436f07911094.tar.gz riscv-isa-manual-297d2021fa86e9217f412f8c6c7e436f07911094.tar.bz2 | |
Misaligned superpage exception occurs if pte.ppn[i−1:0]!=0
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index de6656b..a862549 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1241,7 +1241,7 @@ follows: the {\tt mstatus} register. If not, stop and raise a page-fault exception corresponding to the original access type. -\item If $i>0$ and $pa.ppn[i-1:0]\neq 0$, this is a misaligned superpage; +\item If $i>0$ and $pte.ppn[i-1:0]\neq 0$, this is a misaligned superpage; stop and raise a page-fault exception corresponding to the original access type. \item If $pte.a=0$, or if the memory access is a store and $pte.d=0$, either |