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| author | Andrew Waterman <andrew@sifive.com> | 2018-04-25 20:57:34 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-04-25 20:57:34 -0700 |
| commit | 1400e614a790fc4b9ef0f89b69acaeab8a7d0207 (patch) | |
| tree | f7f99d9b90ed15deee162ed0f3e291230826699c /src/supervisor.tex | |
| parent | ba5cfa4d1eb0aeb9e694dbaf6ccb05312cca02b0 (diff) | |
| download | riscv-isa-manual-1400e614a790fc4b9ef0f89b69acaeab8a7d0207.zip riscv-isa-manual-1400e614a790fc4b9ef0f89b69acaeab8a7d0207.tar.gz riscv-isa-manual-1400e614a790fc4b9ef0f89b69acaeab8a7d0207.tar.bz2 | |
SvXX instruction addresses are checked for sign extension, too
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index a862549..15c33e8 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1288,7 +1288,8 @@ the size of hardware structures that store virtual addresses. Sv39 implementations support a 39-bit virtual address space, divided into \wunits{4}{KiB} pages. An Sv39 address is partitioned as -shown in Figure~\ref{sv39va}. Load and store effective addresses, +shown in Figure~\ref{sv39va}. +Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63--39 all equal to bit 38, or else a page-fault exception will occur. The 27-bit VPN is translated into a 44-bit PPN via a three-level page table, while the 12-bit page offset @@ -1433,7 +1434,8 @@ Sv39. Sv48 implementations support a 48-bit virtual address space, divided into \wunits{4}{KiB} pages. An Sv48 address is partitioned as -shown in Figure~\ref{sv48va}. Load and store effective addresses, +shown in Figure~\ref{sv48va}. +Instruction fetch addresses and load and store effective addresses, which are 64 bits, must have bits 63--48 all equal to bit 47, or else a page-fault exception will occur. The 36-bit VPN is translated into a 44-bit PPN via a four-level page table, while the 12-bit page offset |