Mostly remove RV128 from priv spec, for now

1 files changed, 4 insertions, 4 deletions

diff --git a/src/supervisor.tex b/src/supervisor.tex
index b83c4de..2087c39 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -38,7 +38,7 @@ the supervisor-level CSR descriptions.
 
 The {\tt sstatus} register is an SXLEN-bit read/write register
 formatted as shown in Figure~\ref{sstatusreg-rv32} for RV32 and
-Figure~\ref{sstatusreg} for RV64 and RV128.  The {\tt sstatus}
+Figure~\ref{sstatusreg} for RV64.  The {\tt sstatus}
 register keeps track of the processor's current operating state.
 
 \begin{figure*}[h!]
@@ -146,7 +146,7 @@ register keeps track of the processor's current operating state.
 \end{center}
 }
 \vspace{-0.1in}
-\caption{Supervisor-mode status register ({\tt sstatus}) for RV64 and RV128.}
+\caption{Supervisor-mode status register ({\tt sstatus}) for RV64.}
 \label{sstatusreg}
 \end{figure*}
 
@@ -189,8 +189,8 @@ which may differ from the value of XLEN for S-mode, termed {\em SXLEN}.  The
 encoding of UXL is the same as that of the MXL field of {\tt misa}, shown in
 Table~\ref{misabase}.
 
-For RV32 systems, the UXL field does not exist, and UXLEN=32.  For RV64 and
-RV128 systems, it is a \warl\ field that encodes the current value of UXLEN.
+For RV32 systems, the UXL field does not exist, and UXLEN=32.  For RV64
+systems, it is a \warl\ field that encodes the current value of UXLEN.
 In particular, the implementation may hardwire UXL so that UXLEN=SXLEN.
 
 If UXLEN~$\ne$~SXLEN, instructions executed in the narrower mode must ignore