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| author | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-09-24 00:28:16 -0700 |
|---|---|---|
| committer | Krste Asanovic <krste@eecs.berkeley.edu> | 2018-09-24 00:28:16 -0700 |
| commit | 4c6ee856fcd8576d582a14b55fdab4e72483a804 (patch) | |
| tree | 1992f6175f35024a238a40ba37ad7a614bd33a67 /src/supervisor.tex | |
| parent | 47acba09a4e2e42dbe426b7e69156b28d2a12f50 (diff) | |
| download | riscv-isa-manual-4c6ee856fcd8576d582a14b55fdab4e72483a804.zip riscv-isa-manual-4c6ee856fcd8576d582a14b55fdab4e72483a804.tar.gz riscv-isa-manual-4c6ee856fcd8576d582a14b55fdab4e72483a804.tar.bz2 | |
Made clear that sepc written on exception or interrupt.
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 063ee6d..fa9aaa0 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -557,10 +557,10 @@ and virtual addresses. It need not be capable of holding all possible invalid addresses. Implementations may convert some invalid address patterns into other invalid addresses prior to writing them to {\tt sepc}. -When a trap is taken into S-mode, {\tt sepc} is written with the virtual -address of the instruction that encountered the exception. Otherwise, -{\tt sepc} is never written by the implementation, though it may be -explicitly written by software. +When a trap is taken into S-mode, {\tt sepc} is written with the +virtual address of the instruction that encountered the exception or +was interrupted. Otherwise, {\tt sepc} is never written by the +implementation, though it may be explicitly written by software. \begin{figure}[h!] {\footnotesize |