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authorDaniel Lustig <dlustig@nvidia.com>2021-09-15 09:27:10 -0400
committerDaniel Lustig <dlustig@nvidia.com>2021-09-15 09:27:10 -0400
commit4cdd2e1a8980ac546c45692a7f9e3bda1dcb0a60 (patch)
tree15b9d7a290b7684f6f0ddec4a35fac9eee8ad479 /src/supervisor.tex
parentd56ebd93054aab5ef60812b9d22f618380e086a3 (diff)
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Svpbmt arch review
* Restore Svpbmt mode names * Add note about Zicbom
Diffstat (limited to 'src/supervisor.tex')
-rw-r--r--src/supervisor.tex28
1 files changed, 16 insertions, 12 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 93c833c..4150084 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -2273,14 +2273,14 @@ pages. The encoding for the PBMT bits is captured in Table~\ref{pbmt}.
\begin{table*}[h!]
\begin{center}
-\begin{tabular}{|r|l|}
+\begin{tabular}{|c|c|l|}
\hline
-Value & Requested Memory Attributes \\
+Mode & Value & Requested Memory Attributes \\
\hline
-0 & None \\
-1 & Non-cacheable, idempotent, weakly-ordered (RVWMO or RVTSO), main memory \\
-2 & Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O \\
-3 & {\em Reserved for future standard use} \\
+PMA & 0 & None \\
+NC & 1 & Non-cacheable, idempotent, weakly-ordered (RVWMO or RVTSO), main memory \\
+IO & 2 & Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O \\
+$-$ & 3 & {\em Reserved for future standard use} \\
\hline
\end{tabular}
\end{center}
@@ -2298,20 +2298,20 @@ For non-leaf PTEs, bits 62--61 are reserved for future standard use and must be
cleared by software for forward compatibility.
If the underlying physical memory attribute for a page is main memory and
-the page has PBMT=0 or PBMT=1, or if the underlying physical memory attribute
-for a page is I/O and the page has PBMT=0 or PBMT=2, then accesses to that page
+the page has PBMT=PMA or PBMT=NC, or if the underlying physical memory attribute
+for a page is I/O and the page has PBMT=PMA or PBMT=IO, then accesses to that page
obey the same memory ordering rules normally applied to accesses to that
physical page.
If the underlying physical memory attribute for a page is I/O, and the page has
-PBMT=1, then then accesses to that page obey RVWMO. Accesses to such pages are
+PBMT=NC, then then accesses to that page obey RVWMO. Accesses to such pages are
considered main memory rather than I/O for the purposes of FENCE, {\em.aq}, and
{\em.rl}.
If the underlying physical memory attribute for a page is main memory, and the
-page has PBMT=2, then accesses to that page obey strong channel 0 I/O ordering
+page has PBMT=IO, then accesses to that page obey strong channel 0 I/O ordering
rules with respect to other accesses to physical main memory and to other
-accesses to pages with PBMT=2. Furthermore, accesses to such pages are
+accesses to pages with PBMT=IO. Furthermore, accesses to such pages are
considered I/O rather than main memory for the purposes of FENCE, {\em.aq}, and
{\em.rl}.
@@ -2333,6 +2333,10 @@ be evicted from the cache by the latter. If on the other hand the cacheable
access appears after the non-cacheable access, then the former may remain
cached as it normally would.
+The forthcoming Zicbom extension and the FENCE instruction will collectively
+form a standard mechanism for restoring coherence in scenarios with
+mismatched page attributes.
+
Likewise, accesses performed under memory indicating the non-idempotent
attribute must not be merged with idempotent accesses to the same region
in flight at the same time, as the non-idempotency of the former must
@@ -2350,7 +2354,7 @@ A device driver written to rely on I/O strong ordering rules will not
operate correctly if the address range is mapped as main memory by the
page-based memory types. As such, this configuration is discouraged.
-It will often still be useful to map physical I/O regions using PBMT=1 so that
+It will often still be useful to map physical I/O regions using PBMT=NC so that
write combining and speculative accesses can be performed. Such optimizations
will likely improve performance when applied with adequate care.
\end{commentary}