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authorAndrew Waterman <andrew@sifive.com>2024-02-12 01:20:11 -0800
committerAndrew Waterman <andrew@sifive.com>2024-02-12 01:20:11 -0800
commit1d306d0a3eacc421f652c849de8c55f70fe8d231 (patch)
treea65d8b3ef4b741bc7b4db3b9928f23c92a02ccee /src/supervisor.adoc
parent371b75f7ad80512d5570765dbc804ba89e21fe2d (diff)
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Incorporate mie/mip aspect of Sscofpmf
Diffstat (limited to 'src/supervisor.adoc')
-rw-r--r--src/supervisor.adoc15
1 files changed, 12 insertions, 3 deletions
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index f90ef5c..a9e449b 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -287,6 +287,15 @@ interrupt-enable bits for supervisor-level software interrupts. If
implemented, SSIP is writable in `sip` and may also be set to 1 by a
platform-specific interrupt controller.
+If the Sscofpmf extension is implemented, bits `sip`.LCOFIP and `sie`.LCOFIE
+are the interrupt-pending and interrupt-enable bits for local counter-overflow
+interrupts.
+LCOFIP is read-write in `sip` and reflects the occurrence of a local
+counter-overflow overflow interrupt request resulting from any of the
+`mhpmevent__n__`.OF bits being set.
+If the Sscofpmf extension is not implemented, `sip`.LCOFIP and `sie`.LCOFIE are
+read-only zeros.
+
[NOTE]
====
Interprocessor interrupts are sent to other harts by
@@ -294,7 +303,7 @@ implementation-specific means, which will ultimately cause the SSIP bit
to be set in the recipient hart’s `sip` register.
====
-Each standard interrupt type (SEI, STI, or SSI) may not be implemented,
+Each standard interrupt type (SEI, STI, SSI, or LCOFI) may not be implemented,
in which case the corresponding interrupt-pending and interrupt-enable
bits are read-only zeros. All bits in `sip` and `sie` are *WARL* fields. The
implemented interrupts may be found by writing one to every bit location
@@ -315,7 +324,7 @@ M-mode to S-mode, they are shown as 0 in
====
Multiple simultaneous interrupts destined for supervisor mode are
-handled in the following decreasing priority order: SEI, SSI, STI.
+handled in the following decreasing priority order: SEI, SSI, STI, LCOFI.
==== Supervisor Timers and Performance Counters
@@ -445,7 +454,7 @@ Supervisor timer interrupt +
_Reserved_ +
Supervisor external interrupt +
_Reserved_ +
-_Reserved for counter-overflow interrupt_ +
+Counter-overflow interrupt +
_Reserved_ +
_Designated for platform use_