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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2018-10-09 16:35:55 -0700 |
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committer | Andrew Waterman <aswaterman@gmail.com> | 2018-10-09 16:35:55 -0700 |
commit | a69590d9b4f55adec829960b04ccc4e14dbad6da (patch) | |
tree | ae79e8e242bfa0f2cdf856fa981712b1a81f4b28 /src/rvwmo.tex | |
parent | efdf5daee7ce3eb5821bb40e847b948b6126e601 (diff) | |
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Some edits and fixes to memory model sections. (#238)
* Some edits and fixes to memory model sections.
* Also fix a typo spotted by @daniellustig.
Diffstat (limited to 'src/rvwmo.tex')
-rw-r--r-- | src/rvwmo.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rvwmo.tex b/src/rvwmo.tex index d289c13..70e9e14 100644 --- a/src/rvwmo.tex +++ b/src/rvwmo.tex @@ -192,7 +192,7 @@ An execution of a RISC-V program obeys the RVWMO memory consistency model only i \end{enumerate} } -\newcommand{\atomicityaxiom}{If $r$ and $w$ are paired load and store operations generated by aligned LR and SC instructions in a hart $h$, $s$ is a store to byte $x$, and $r$ returns a value written by $s$, then $s$ must precede $w$ in the global memory order, and there can be no store from hart other than $h$ to byte $x$ following $s$ and preceding $w$ in the global memory order.} +\newcommand{\atomicityaxiom}{If $r$ and $w$ are paired load and store operations generated by aligned LR and SC instructions in a hart $h$, $s$ is a store to byte $x$, and $r$ returns a value written by $s$, then $s$ must precede $w$ in the global memory order, and there can be no store from a hart other than $h$ to byte $x$ following $s$ and preceding $w$ in the global memory order.} \newcommand{\progressaxiom}{No memory operation may be preceded in the global memory order by an infinite sequence of other memory operations.} |