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author | elisa <elisa@riscv.org> | 2021-09-28 09:26:30 -0700 |
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committer | elisa <elisa@riscv.org> | 2021-09-28 09:26:30 -0700 |
commit | c755f05b62e435e43de88abf4b68b1575e239957 (patch) | |
tree | 89f7f4cbe788006f4a9cb2ef40a8e5b06b9cde47 /src/rvwmo.adoc | |
parent | 937f16832c71e9b1c794fe02a11c7ebb7837ead8 (diff) | |
download | riscv-isa-manual-c755f05b62e435e43de88abf4b68b1575e239957.zip riscv-isa-manual-c755f05b62e435e43de88abf4b68b1575e239957.tar.gz riscv-isa-manual-c755f05b62e435e43de88abf4b68b1575e239957.tar.bz2 |
some table fixes and additions of missing formatting
Diffstat (limited to 'src/rvwmo.adoc')
-rw-r--r-- | src/rvwmo.adoc | 196 |
1 files changed, 93 insertions, 103 deletions
diff --git a/src/rvwmo.adoc b/src/rvwmo.adoc index e6bc412..76559c3 100644 --- a/src/rvwmo.adoc +++ b/src/rvwmo.adoc @@ -273,17 +273,17 @@ latexmath:[$a$] and latexmath:[$b$] both access regular main memory * Overlapping-Address Orderings: . latexmath:[$b$] is a store, and latexmath:[$a$] and latexmath:[$b$] access overlapping memory addresses -. [#ppo:rdw]#[ppo:rdw]# latexmath:[$a$] and latexmath:[$b$] are loads, +. latexmath:[$a$] and latexmath:[$b$] are loads, latexmath:[$x$] is a byte read by both latexmath:[$a$] and latexmath:[$b$], there is no store to latexmath:[$x$] between latexmath:[$a$] and latexmath:[$b$] in program order, and latexmath:[$a$] and latexmath:[$b$] return values for latexmath:[$x$] written by different memory operations -. {empty}[#ppo:amoforward]#[ppo:amoforward]# latexmath:[$a$] is +. latexmath:[$a$] is generated by an AMO or SC instruction, latexmath:[$b$] is a load, and latexmath:[$b$] returns a value written by latexmath:[$a$] * Explicit Synchronization -. {empty} There is a FENCE instruction that +. There is a FENCE instruction that orders latexmath:[$a$] before latexmath:[$b$] . latexmath:[$a$] has an acquire annotation @@ -293,19 +293,19 @@ RCsc annotations . {empty} latexmath:[$a$] is paired with latexmath:[$b$] * Syntactic Dependencies -. {empty} latexmath:[$b$] has a syntactic address +. latexmath:[$b$] has a syntactic address dependency on latexmath:[$a$] -. {empty} latexmath:[$b$] has a syntactic data +. latexmath:[$b$] has a syntactic data dependency on latexmath:[$a$] -. {empty} latexmath:[$b$] is a store, and +. latexmath:[$b$] is a store, and latexmath:[$b$] has a syntactic control dependency on latexmath:[$a$] * Pipeline Dependencies -. {empty} latexmath:[$b$] is a +. latexmath:[$b$] is a load, and there exists some store latexmath:[$m$] between latexmath:[$a$] and latexmath:[$b$] in program order such that latexmath:[$m$] has an address or data dependency on latexmath:[$a$], and latexmath:[$b$] returns a value written by latexmath:[$m$] -. {empty} latexmath:[$b$] is a store, and +. latexmath:[$b$] is a store, and there exists some instruction latexmath:[$m$] between latexmath:[$a$] and latexmath:[$b$] in program order such that latexmath:[$m$] has an address dependency on latexmath:[$a$] @@ -398,53 +398,52 @@ any source register to any destination register latexmath:[$^\ddagger$]The instruction carries dependencies from source register(s) to destination register(s) as specified -[cols="<,<,<,<,<",] +[cols="<,<,<,<",] |=== -|*RV32I Base Integer Instruction Set* | | | | -| |Source |Destination |Accumulating | -| |Registers |Registers |CSRs | -|LUI | |_rd_ | | -|AUIPC | |_rd_ | | -|JAL | |_rd_ | | -|JALRlatexmath:[$^\dagger$] |_rs1_ |_rd_ | | -|BEQ |_rs1_, _rs2_ | | | -|BNE |_rs1_, _rs2_ | | | -|BLT |_rs1_, _rs2_ | | | -|BGE |_rs1_, _rs2_ | | | -|BLTU |_rs1_, _rs2_ | | | -|BGEU |_rs1_, _rs2_ | | | -|LBlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | | -|LHlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | | -|LWlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | | -|LBUlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | | -|LHUlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | | -|SB |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | | -|SH |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | | -|SW |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | | -|ADDI |_rs1_ |_rd_ | | -|SLTI |_rs1_ |_rd_ | | -|SLTIU |_rs1_ |_rd_ | | -|XORI |_rs1_ |_rd_ | | -|ORI |_rs1_ |_rd_ | | -|ANDI |_rs1_ |_rd_ | | -|SLLI |_rs1_ |_rd_ | | -|SRLI |_rs1_ |_rd_ | | -|SRAI |_rs1_ |_rd_ | | -|ADD |_rs1_, _rs2_ |_rd_ | | -|SUB |_rs1_, _rs2_ |_rd_ | | -|SLL |_rs1_, _rs2_ |_rd_ | | -|SLT |_rs1_, _rs2_ |_rd_ | | -|SLTU |_rs1_, _rs2_ |_rd_ | | -|XOR |_rs1_, _rs2_ |_rd_ | | -|SRL |_rs1_, _rs2_ |_rd_ | | -|SRA |_rs1_, _rs2_ |_rd_ | | -|OR |_rs1_, _rs2_ |_rd_ | | -|AND |_rs1_, _rs2_ |_rd_ | | -|FENCE | | | | -|FENCE.I | | | | -|ECALL | | | | -|EBREAK | | | | -| | | | | +|*RV32I Base Integer Instruction Set* | | | +| |Source |Destination |Accumulating +| |Registers |Registers |CSRs +|LUI | |_rd_ | +|AUIPC | |_rd_ | +|JAL | |_rd_ | +|JALRlatexmath:[$^\dagger$] |_rs1_ |_rd_ | +|BEQ |_rs1_, _rs2_ | | +|BNE |_rs1_, _rs2_ | | +|BLT |_rs1_, _rs2_ | | +|BGE |_rs1_, _rs2_ | | +|BLTU |_rs1_, _rs2_ | | +|BGEU |_rs1_, _rs2_ | | +|LBlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | +|LHlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | +|LWlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | +|LBUlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | +|LHUlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | +|SB |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | +|SH |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | +|SW |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | +|ADDI |_rs1_ |_rd_ | +|SLTI |_rs1_ |_rd_ | +|SLTIU |_rs1_ |_rd_ | +|XORI |_rs1_ |_rd_ | +|ORI |_rs1_ |_rd_ | +|ANDI |_rs1_ |_rd_ | +|SLLI |_rs1_ |_rd_ | +|SRLI |_rs1_ |_rd_ | +|SRAI |_rs1_ |_rd_ | +|ADD |_rs1_, _rs2_ |_rd_ | +|SUB |_rs1_, _rs2_ |_rd_ | +|SLL |_rs1_, _rs2_ |_rd_ | +|SLT |_rs1_, _rs2_ |_rd_ | +|SLTU |_rs1_, _rs2_ |_rd_ | +|XOR |_rs1_, _rs2_ |_rd_ | +|SRL |_rs1_, _rs2_ |_rd_ | +|SRA |_rs1_, _rs2_ |_rd_ | +|OR |_rs1_, _rs2_ |_rd_ | +|AND |_rs1_, _rs2_ |_rd_ | +|FENCE | | | +|FENCE.I | | | +|ECALL | | | +|EBREAK | | | |=== [cols="<,<,<,<,<",] @@ -488,56 +487,53 @@ from _csr_ to _rd_ | | | | |latexmath:[$\ddagger$]carries a dependency from _csr_ to _rd_ | | | |=== -[cols="<,<,<,<,<",] +[cols="<,<,<,<",] |=== -|*RV64I Base Integer Instruction Set* | | | | -| |Source |Destination |Accumulating | -| |Registers |Registers |CSRs | -|LWUlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | | -|LDlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | | -|SD |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | | -|SLLI |_rs1_ |_rd_ | | -|SRLI |_rs1_ |_rd_ | | -|SRAI |_rs1_ |_rd_ | | -|ADDIW |_rs1_ |_rd_ | | -|SLLIW |_rs1_ |_rd_ | | -|SRLIW |_rs1_ |_rd_ | | -|SRAIW |_rs1_ |_rd_ | | -|ADDW |_rs1_, _rs2_ |_rd_ | | -|SUBW |_rs1_, _rs2_ |_rd_ | | -|SLLW |_rs1_, _rs2_ |_rd_ | | -|SRLW |_rs1_, _rs2_ |_rd_ | | -|SRAW |_rs1_, _rs2_ |_rd_ | | -| | | | | +|*RV64I Base Integer Instruction Set* | | | +| |Source |Destination |Accumulating +| |Registers |Registers |CSRs +|LWUlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | +|LDlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$] |_rd_ | +|SD |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] | | +|SLLI |_rs1_ |_rd_ | +|SRLI |_rs1_ |_rd_ | +|SRAI |_rs1_ |_rd_ | +|ADDIW |_rs1_ |_rd_ | +|SLLIW |_rs1_ |_rd_ | +|SRLIW |_rs1_ |_rd_ | +|SRAIW |_rs1_ |_rd_ | +|ADDW |_rs1_, _rs2_ |_rd_ | +|SUBW |_rs1_, _rs2_ |_rd_ | +|SLLW |_rs1_, _rs2_ |_rd_ | +|SRLW |_rs1_, _rs2_ |_rd_ | +|SRAW |_rs1_, _rs2_ |_rd_ | |=== -[cols="<,<,<,<,<",] +[cols="<,<,<,<",] |=== -|*RV32M Standard Extension* | | | | -| |Source |Destination |Accumulating | -| |Registers |Registers |CSRs | -|MUL |_rs1_, _rs2_ |_rd_ | | -|MULH |_rs1_, _rs2_ |_rd_ | | -|MULHSU |_rs1_, _rs2_ |_rd_ | | -|MULHU |_rs1_, _rs2_ |_rd_ | | -|DIV |_rs1_, _rs2_ |_rd_ | | -|DIVU |_rs1_, _rs2_ |_rd_ | | -|REM |_rs1_, _rs2_ |_rd_ | | -|REMU |_rs1_, _rs2_ |_rd_ | | -| | | | | +|*RV32M Standard Extension* | | | +| |Source |Destination |Accumulating +| |Registers |Registers |CSRs +|MUL |_rs1_, _rs2_ |_rd_ | +|MULH |_rs1_, _rs2_ |_rd_ | +|MULHSU |_rs1_, _rs2_ |_rd_ | +|MULHU |_rs1_, _rs2_ |_rd_ | +|DIV |_rs1_, _rs2_ |_rd_ | +|DIVU |_rs1_, _rs2_ |_rd_ | +|REM |_rs1_, _rs2_ |_rd_ | +|REMU |_rs1_, _rs2_ |_rd_ | |=== -[cols="<,<,<,<,<",] +[cols="<,<,<,<",] |=== -|*RV64M Standard Extension* | | | | -| |Source |Destination |Accumulating | -| |Registers |Registers |CSRs | -|MULW |_rs1_, _rs2_ |_rd_ | | -|DIVW |_rs1_, _rs2_ |_rd_ | | -|DIVUW |_rs1_, _rs2_ |_rd_ | | -|REMW |_rs1_, _rs2_ |_rd_ | | -|REMUW |_rs1_, _rs2_ |_rd_ | | -| | | | | +|*RV64M Standard Extension* | | | +| |Source |Destination |Accumulating +| |Registers |Registers |CSRs +|MULW |_rs1_, _rs2_ |_rd_ | +|DIVW |_rs1_, _rs2_ |_rd_ | +|DIVUW |_rs1_, _rs2_ |_rd_ | +|REMW |_rs1_, _rs2_ |_rd_ | +|REMUW |_rs1_, _rs2_ |_rd_ | |=== [cols="<,<,<,<,<",] @@ -581,7 +577,6 @@ _rs2_latexmath:[$^D$] |_rd_ | | |AMOMAXU.Wlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] |_rd_ | | -| | | | | |=== [cols="<,<,<,<,<",] @@ -625,7 +620,6 @@ _rs2_latexmath:[$^D$] |_rd_ | | |AMOMAXU.Dlatexmath:[$^\dagger$] |_rs1_latexmath:[$^A$], _rs2_latexmath:[$^D$] |_rd_ | | -| | | | | |=== [cols="<,<,<,<,<",] @@ -701,7 +695,6 @@ rm=111 |FMV.W.X |_rs1_ |_rd_ | | -| | | | | |=== [cols="<,<,<,<,<",] @@ -724,7 +717,6 @@ rm=111 |FCVT.S.LU |_rs1_, frmlatexmath:[$^*$] |_rd_ |NX |latexmath:[$^*$]if rm=111 -| | | | | |=== [cols="<,<,<,<,<",] @@ -799,7 +791,6 @@ rm=111 |FCVT.D.WU |_rs1_ |_rd_ | | -| | | | | |=== [cols="<,<,<,<,<",] @@ -826,6 +817,5 @@ rm=111 |FMV.D.X |_rs1_ |_rd_ | | -| | | | | |=== |