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| author | Andrew Waterman <andrew@sifive.com> | 2019-03-25 01:46:28 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-25 01:54:01 -0700 |
| commit | 825c9395021ad25ae0726afa91a9a4f27daec2dc (patch) | |
| tree | f8f20a665f2f66792ff0dfbd8eef92ec25ddbcb4 /src/rv64.tex | |
| parent | e4c8a3875a5f74f2c3bff7b93ff2dbbf2f6ebb25 (diff) | |
| download | riscv-isa-manual-825c9395021ad25ae0726afa91a9a4f27daec2dc.zip riscv-isa-manual-825c9395021ad25ae0726afa91a9a4f27daec2dc.tar.gz riscv-isa-manual-825c9395021ad25ae0726afa91a9a4f27daec2dc.tar.bz2 | |
Change "pc" to "address" for clarity
Resolves #356
Diffstat (limited to 'src/rv64.tex')
| -rw-r--r-- | src/rv64.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/rv64.tex b/src/rv64.tex index ef51e62..bde375c 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -139,11 +139,11 @@ places zero in the lowest 12 bits. The 32-bit result is sign-extended to 64 bits. AUIPC (add upper immediate to {\tt pc}) uses the same opcode as RV32I. -AUIPC (add upper immediate to {\tt pc}) is used to build {\tt +AUIPC is used to build {\tt pc}-relative addresses and uses the U-type format. AUIPC appends 12 low-order zero bits to the 20-bit U-immediate, sign-extends the result -to 64 bits, then adds it to the {\tt pc} and places the result in -register {\em rd}. +to 64 bits, adds it to the address of the AUIPC instruction, +then places the result in register {\em rd}. \subsubsection*{Integer Register-Register Operations} |