Standardized on pseudoinstruction.

Closes #122

1 files changed, 2 insertions, 2 deletions

diff --git a/src/rv64.tex b/src/rv64.tex
index 5de9ea2..903c1dc 100644
--- a/src/rv64.tex
+++ b/src/rv64.tex
@@ -61,7 +61,7 @@ immediate to register {\em rs1} and produces the proper sign-extension
 of a 32-bit result in {\em rd}.  Overflows are ignored and the result
 is the low 32 bits of the result sign-extended to 64 bits.  Note,
 ADDIW {\em rd, rs1, 0} writes the sign-extension of the lower 32 bits
-of register {\em rs1} into register {\em rd} (assembler pseudo-op
+of register {\em rs1} into register {\em rd} (assembler psuedo-instruction
 SEXT.W).
 
 \vspace{-0.2in}
@@ -247,7 +247,7 @@ low bits of register {\em rs2} to memory respectively.
 \section{System Instructions}
 
 In RV64I, the CSR instructions can manipulate 64-bit CSRs.  In particular, the
-RDCYCLE, RDTIME, and RDINSTRET pseudo-instructions read the full 64 bits of
+RDCYCLE, RDTIME, and RDINSTRET pseudoinstructions read the full 64 bits of
 the {\tt cycle}, {\tt time}, and {\tt instret} counters.  Hence, the RDCYCLEH,
 RDTIMEH, and RDINSTRETH instructions are not necessary and are illegal in
 RV64I.