Improve description of RV64 *W instructions

1 files changed, 8 insertions, 7 deletions

diff --git a/src/rv64.tex b/src/rv64.tex
index 2d25d95..3d71fde 100644
--- a/src/rv64.tex
+++ b/src/rv64.tex
@@ -17,8 +17,8 @@ Most integer computational instructions operate on XLEN-bit values.
 Additional instruction variants are provided to manipulate 32-bit
 values in RV64I, indicated by a `W' suffix to the opcode.  These
 ``*W'' instructions ignore the upper 32 bits of their inputs and
-always produce 32-bit signed values, i.e. bits XLEN-1 through 31 are
-equal.
+always produce 32-bit signed values, sign-extending them to 64 bits,
+i.e. bits XLEN-1 through 31 are equal.
 
 \begin{commentary}
 The compiler and calling convention maintain an invariant that all 32-bit
@@ -105,9 +105,9 @@ into the upper bits); and SRAI is an arithmetic right shift (the
 original sign bit is copied into the vacated upper bits).
 
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are
-analogously defined but operate on 32-bit values and produce
-signed 32-bit results.  SLLIW, SRLIW, and SRAIW encodings
-with $imm[5] \neq 0$ are reserved.
+analogously defined but operate on 32-bit values and
+sign-extend their 32-bit results to 64 bits.
+SLLIW, SRLIW, and SRAIW encodings with $imm[5] \neq 0$ are reserved.
 
 \begin{commentary}
   Previously, SLLIW, SRLIW, and SRAIW with $imm[5] \neq 0$ were defined to
@@ -192,8 +192,9 @@ held in register {\em rs2}.  In RV64I, only the low 6 bits of {\em
   rs2} are considered for the shift amount.
 
 SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously
-defined but operate on 32-bit values and produce signed 32-bit
-results.  The shift amount is given by {\em rs2[4:0]}.
+defined but operate on 32-bit values and
+sign-extend their 32-bit results to 64 bits.
+The shift amount is given by {\em rs2[4:0]}.
 
 \section{Load and Store Instructions}