Merge pull request #453 from riscv/u-immediate

Consistently claim that U-immediate is 32 bits, not 20 bits

1 files changed, 7 insertions, 6 deletions

diff --git a/src/rv64.tex b/src/rv64.tex
index 9321ac4..24e78b1 100644
--- a/src/rv64.tex
+++ b/src/rv64.tex
@@ -134,15 +134,16 @@ U-immediate[31:12] & dest & AUIPC
 \end{center}
 
 LUI (load upper immediate) uses the same opcode as RV32I.  LUI places
-the 20-bit U-immediate into bits 31--12 of register {\em rd} and
-places zero in the lowest 12 bits.  The 32-bit result is
-sign-extended to 64 bits.
+the 32-bit U-immediate into register {\em rd}, filling in the lowest 12
+bits with zeros.
+The 32-bit result is sign-extended to 64 bits.
 
 AUIPC (add upper immediate to {\tt pc}) uses the same opcode as RV32I.
 AUIPC is used to build {\tt
-  pc}-relative addresses and uses the U-type format.  AUIPC appends 12
-low-order zero bits to the 20-bit U-immediate, sign-extends the result
-to 64 bits, adds it to the address of the AUIPC instruction,
+  pc}-relative addresses and uses the U-type format.  AUIPC forms a 32-bit
+offset from the U-immediate, filling in the lowest 12 bits with zeros,
+sign-extends the result to 64 bits,
+adds it to the address of the AUIPC instruction,
 then places the result in register {\em rd}.
 
 \subsubsection*{Integer Register-Register Operations}