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author | Andrew Waterman <andrew@sifive.com> | 2019-10-19 14:10:43 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2019-10-19 14:15:15 -0700 |
commit | 0ac0b9a801299896f20aaa69744e246e71204150 (patch) | |
tree | a05d6cdb08d81a71b4bc8408986cc12652ae6f06 /src/rv64.tex | |
parent | acbb41226286e052e62891c6473abe7718a21b44 (diff) | |
download | riscv-isa-manual-0ac0b9a801299896f20aaa69744e246e71204150.zip riscv-isa-manual-0ac0b9a801299896f20aaa69744e246e71204150.tar.gz riscv-isa-manual-0ac0b9a801299896f20aaa69744e246e71204150.tar.bz2 |
Consistently claim that U-immediate is 32 bits, not 20 bits
The text vacillates between describing the U-immediate as a 20-bit
quantity, and as a 32-bit quantity whose lower 12 bits are zero.
Standardize on the latter. Note the discrepancy in the ASM syntax.
Resolves #452
Diffstat (limited to 'src/rv64.tex')
-rw-r--r-- | src/rv64.tex | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/rv64.tex b/src/rv64.tex index 92a098a..45b6a79 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -134,15 +134,16 @@ U-immediate[31:12] & dest & AUIPC \end{center} LUI (load upper immediate) uses the same opcode as RV32I. LUI places -the 20-bit U-immediate into bits 31--12 of register {\em rd} and -places zero in the lowest 12 bits. The 32-bit result is -sign-extended to 64 bits. +the 32-bit U-immediate into register {\em rd}, filling in the lowest 12 +bits with zeros. +The 32-bit result is sign-extended to 64 bits. AUIPC (add upper immediate to {\tt pc}) uses the same opcode as RV32I. AUIPC is used to build {\tt - pc}-relative addresses and uses the U-type format. AUIPC appends 12 -low-order zero bits to the 20-bit U-immediate, sign-extends the result -to 64 bits, adds it to the address of the AUIPC instruction, + pc}-relative addresses and uses the U-type format. AUIPC forms a 32-bit +offset from the U-immediate, filling in the lowest 12 bits with zeros, +sign-extends the result to 64 bits, +adds it to the address of the AUIPC instruction, then places the result in register {\em rd}. \subsubsection*{Integer Register-Register Operations} |