diff options
| author | Andrew Waterman <andrew@sifive.com> | 2019-03-07 13:42:32 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-03-07 13:42:32 -0800 |
| commit | f3663bddccd838842154aed6db44d93dfc19d009 (patch) | |
| tree | 041400ca5b4dd0c852e50be0069d7eab8ca17dcd /src/rv64.tex | |
| parent | 47ca7ce69c566b4c59923d87ce7c1875f4ff4b80 (diff) | |
| download | riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.zip riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.tar.gz riscv-isa-manual-f3663bddccd838842154aed6db44d93dfc19d009.tar.bz2 | |
Tweaks suggested by Bill Huffman
Diffstat (limited to 'src/rv64.tex')
| -rw-r--r-- | src/rv64.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/rv64.tex b/src/rv64.tex index d9bda29..ef51e62 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -110,7 +110,7 @@ signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with $imm[5] \neq 0$ are reserved. \begin{commentary} - Previously, SLLIW, SRLIW, and SRAIW with imm[5]=0 were defined to + Previously, SLLIW, SRLIW, and SRAIW with $imm[5] \neq 0$ were defined to cause illegal instruction exceptions, whereas now they are marked as reserved. This is a backwards-compatible change. \end{commentary} |