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| author | Andrew Waterman <andrew@sifive.com> | 2018-10-29 14:37:17 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-10-29 14:37:17 -0700 |
| commit | 67bcecbaecd9a0a665c75c64b0a41bb6186f4ed9 (patch) | |
| tree | 4a1b514bed96496feb3dc92a3b37d65228cf7f06 /src/rv64.tex | |
| parent | 15c872135d33de854a797126d68e5d24b7c18480 (diff) | |
| download | riscv-isa-manual-67bcecbaecd9a0a665c75c64b0a41bb6186f4ed9.zip riscv-isa-manual-67bcecbaecd9a0a665c75c64b0a41bb6186f4ed9.tar.gz riscv-isa-manual-67bcecbaecd9a0a665c75c64b0a41bb6186f4ed9.tar.bz2 | |
Clarify that most integer instructions operate on XLEN bits in RV64
h/t Olof Kindgren
Resolves #247.
Diffstat (limited to 'src/rv64.tex')
| -rw-r--r-- | src/rv64.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/rv64.tex b/src/rv64.tex index 0aaf127..3fb09f6 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -13,6 +13,7 @@ RV64I widens the integer registers and supported user address space to \section{Integer Computational Instructions} +Most integer computational instructions operate on XLEN-bit values. Additional instruction variants are provided to manipulate 32-bit values in RV64I, indicated by a `W' suffix to the opcode. These ``*W'' instructions ignore the upper 32 bits of their inputs and |